© 2004 Microchip Technology Inc. DS70049C-page 2-23
Section 2. CPU
CPU
2
2.6.3 Data Accumulator Adder/Subtractor
The data accumulators have a 40-bit adder/subtractor with automatic sign extension logic for the
multiplier result (if signed). It can select one of two accumulators (A or B) as its pre-accumulation
source and post-accumulation destination. For the ADD (accumulator) and LAC instructions, the
data to be accumulated or loaded can optionally be scaled via the barrel shifter prior to
accumulation.
The 40-bit adder/subtractor may optionally negate one of its operand inputs to change the sign
of the result (without changing the operands). The negate is used during multiply and subtract
(MSC), or multiply and negate (MPY.N) operations.
The 40-bit adder/subtractor has an additional saturation block which controls accumulator data
saturation, if enabled.
2.6.3.1 Accumulator Status Bits
Six Status register bits have been provided to support saturation and overflow. They are located
in the CPU Status register, SR, and are listed below:
Table 2-5: Accumulator Overflow and Saturation Status Bits
The OA and OB bits are read only and are modified each time data passes through the accumu-
lator add/subtract logic. When set, they indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39). This type of overflow is not catastrophic; the
guard bits preserve the accumulator data. The OAB status bit is the logically ORed value of OA
and OB.
The OA and OB bits, when set, can optionally generate an arithmetic error trap. The trap is
enabled by setting the corresponding overflow trap flag enable bit OVATE:OVBTE
(INTCON1<10:9>). The trap event allows the user to take immediate corrective action, if desired.
The SA and SB bits can be set each time data passes through the accumulator saturation logic.
Once set, these bits remain set until cleared by the user. The SAB status bit indicates the logically
ORed value of SA and SB. The SA and SB bits will be cleared when SAB is cleared. When set,
these bits indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit
saturation or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled).
When saturation is not enabled, the SA and SB bits indicate that a catastrophic overflow has
occurred (the sign of the accumulator has been destroyed). If the COVTE (INTCON1<8>) bit is
set, SA and SB bits will generate an arithmetic error trap when saturation is disabled.
Status Bit Location Description
OA SR<15> Accumulator A overflowed into guard bits (ACCA<39:32>)
OB SR<14> Accumulator B overflowed into guard bits(ACCB<39:32>)
SA SR<13> ACCA saturated (bit 31 overflow and saturation)
or
ACCA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
SB SR<12> ACCB saturated (bit 31 overflow and saturation)
or
ACCB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
OAB SR<11> OA logically ORed with OB
SAB SR<10> SA logically ORed with SB.
Clearing SAB will also clear SA and SB.
Note: See Section 6. “Reset Interrupts” for further information on arithmetic warning
traps.
Note: The user must remember that SA, SB and SAB status bits can have different
meanings depending on whether accumulator saturation is enabled. The
Accumulator Saturation mode is controlled via the CORCON register.
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