dsPIC30F Family Reference Manual
DS70049C-page 2-24 © 2004 Microchip Technology Inc.
2.6.3.2 Saturation and Overflow Modes
The device supports three Saturation and Overflow modes.
1. Accumulator 39-bit Saturation:
In this mode, the saturation logic loads the maximally positive 9.31 value
(0x7FFFFFFFFF), or maximally negative 9.31 value (0x8000000000), into the target
accumulator. The SA or SB bit is set and remains set until cleared by the user. This
Saturation mode is useful for extending the dynamic range of the accumulator.
To configure for this mode of saturation, the ACCSAT(CORCON<4>) bit must be set.
Additionally, the SATA and/or SATB (CORCON<7 and/or 6>) bits must be set to enable
accumulator saturation.
2. Accumulator 31-bit Saturation:
In this mode, the saturation logic loads the maximally positive 1.31 value
(0x007FFFFFFF) or maximally negative 1.31 value (0xFF80000000) into the target
accumulator. The SA or SB bit is set and remains set until cleared by the user. When this
Saturation mode is in effect, the guard bits 32 through 39 are not used, except for
sign-extension of the accumulator value. Consequently, the OA, OB or OAB bits in SR will
never be set.
To configure for this mode of overflow and saturation, the ACCSAT (CORCON<4>) bit
must be cleared. Additionally, the SATA and/or SATB (CORCON<7 and/or 6>) bits must
be set to enable accumulator saturation.
3. Accumulator Catastrophic Overflow:
If the SATA and/or SATB (CORCON<7 and/or 6>) bits are not set, then no saturation
operation is performed on the accumulator and the accumulator is allowed to overflow all
the way up to bit 39 (destroying its sign). If the COVTE bit (INTCON1<8>) is set, a
catastrophic overflow will initiate an arithmetic error trap.
Note that accumulator saturation and overflow detection can only result from the execution of a
DSP instruction that modifies one of the two accumulators via the 40-bit DSP ALU. Saturation
and overflow detection will not take place when the accumulators are accessed as memory
mapped registers via MCU class instructions. Furthermore, the accumulator status bits shown in
Table 2-5 will not be modified. However, the MCU status bits (Z, N, C, OV, DC) will be modified
depending on the MCU instruction that accesses the accumulator.
2.6.3.3 Data Space Write Saturation
In addition to adder/subtractor saturation, writes to data space can be saturated without affecting
the contents of the source accumulator. This feature allows data to be limited while not sacrificing
the dynamic range of the accumulator during intermediate calculation stages. Data space write
saturation is enabled by setting the SATDW control bit (CORCON<5>). Data space write
saturation is enabled by default at a device Reset.
The data space write saturation feature works with the SAC and SAC.R instructions. The value
held in the accumulator is never modified when these instructions are executed. The hardware
takes the following steps to obtain the saturated write result:
1. The read data is scaled based upon the arithmetic shift value specified in the instruction.
2. The scaled data is rounded (SAC.R only).
3. The scaled/rounded value is saturated to a 16-bit result based on the value of the guard
bits. For data values greater than 0x007FFF, the data written to memory is saturated to
the maximum positive 1.15 value, 0x7FFF. For input data less than 0xFF8000, data
written to memory is saturated to the maximum negative 1.15 value, 0x8000.
Note: See Section 6. “Reset Interrupts” for further information on arithmetic error traps.
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