© 2004 Microchip Technology Inc. DS70065C-page 18-5
Section 18. 12-bit A/D Converter
12-bit A/D
Converter
18
Register 18-1: ADCON1: A/D Control Register 1
Upper Byte:
R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
ADON
—ADSIDL— — —FORM<1:0>
bit 15 bit 8
Lower Byte:
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0
HC, HS
R/C-0
HC, HS
SSRC<2:0>
— — ASAM SAMP DONE
bit 7 bit 0
bit 15 ADON: A/D Operating Mode bit
1 = A/D converter module is operating
0 = A/D converter is off
bit 14 Unimplemented: Read as ‘0’
bit 13 ADSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-10 Unimplemented: Read as ‘0’
bit 9-8 FORM<1:0>: Data Output Format bits
11 = Signed fractional (DOUT = sddd dddd dddd 0000)
10 = Fractional (DOUT = dddd dddd dddd 0000)
01 = Signed integer (DOUT = ssss sddd dddd dddd)
00 = Integer (DOUT = 0000 dddd dddd dddd)
bit 7-5 SSRC<2:0>: Conversion Trigger Source Select bits
111 = Internal counter ends sampling and starts conversion (auto convert)
110 = Reserved
101 = Reserved
100 = Reserved
011 = Motor Control PWM interval ends sampling and starts conversion
010 = General purpose Timer3 compare ends sampling and starts conversion
001 = Active transition on INT0 pin ends sampling and starts conversion
000 = Clearing SAMP bit ends sampling and starts conversion
bit 4-3 Unimplemented: Read as ‘0’
bit 2 ASAM: A/D Sample Auto-Start bit
1 = Sampling begins immediately after last conversion completes. SAMP bit is auto set.
0 = Sampling begins when SAMP bit set
bit 1 SAMP: A/D Sample Enable bit
1 = At least one A/D sample/hold amplifier is sampling
0 = A/D sample/hold amplifiers are holding
When ASAM = 0, writing ‘1’ to this bit will start sampling.
When SSRC = 000, writing ‘0’ to this bit will end sampling and start conversion.
bit 0 DONE: A/D Conversion Status bit
1 = A/D conversion is done
0 = A/D conversion is not done
Clearing this bit will not effect any operation in progress.
Cleared by software or start of a new conversion.
Legend:
R = Readable bit W = Writable bit C = Clearable by software
HC = Hardware clear HS = Hardware set U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown