dsPIC30F Family Reference Manual
DS70065C-page 18-6 © 2004 Microchip Technology Inc.
Register 18-2: ADCON2: A/D Control Register 2
Upper Byte:
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0
VCFG<2:0>
— — CSCNA — —
bit 15 bit 8
Lower Byte:
R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BUFS
— SMPI<3:0> BUFM ALTS
bit 7 bit 0
bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits
bit 12 Reserved: User should write ‘0’ to this location
bit 11 Unimplemented: Read as ‘0’
bit 10 CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexer Setting bit
1 = Scan inputs
0 = Do not scan inputs
bit 9-8 Unimplemented: Read as ‘0’
bit 7 BUFS: Buffer Fill Status bit
Only valid when BUFM = 1 (ADRES split into 2 x 8-word buffers)
1 = A/D is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7
0 = A/D is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF
bit 6 Unimplemented: Read as ‘0’
bit 5-2 SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits
1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence
1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence
.....
0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence
0000 = Interrupts at the completion of conversion for each sample/convert sequence
bit 1 BUFM: Buffer Mode Select bit
1 = Buffer configured as two 8-word buffers ADCBUF(15...8), ADCBUF(7...0)
0 = Buffer configured as one 16-word buffer ADCBUF(15...0)
bit 0 ALTS: Alternate Input Sample Mode Select bit
1 = Uses MUX A input multiplexer settings for first sample, then alternate between MUX B and MUX A input
multiplexer settings for all subsequent samples
0 = Always use MUX A input multiplexer settings
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
A/D VREFHA/D VREFL
000
AVDD AVSS
001
External VREF+ pin AVSS
010
AVDD External VREF- pin
011
External VREF+ pin External VREF- pin
1xx
AVDD AVSS
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