© 2004 Microchip Technology Inc. DS70049C-page 2-29
Section 2. CPU
CPU
2
5. Table Read/Write Instructions:
These instructions will suspend fetching to insert a read or write cycle to the program
memory. The instruction fetched while executing the table operation is saved for 1 cycle and
executed in the cycle immediately after the table operation as shown in Figure 2-17.
Figure 2-17: Instruction Pipeline Flow – Table Operations
6. 2 Instruction Words, 2 Instruction Cycles:
In these instructions, the fetch after the instruction contains data. This results in a 2-cycle
instruction as shown in Figure 2-18. The second word of a two-word instruction is encoded
so that it will be executed as a NOP, should it be fetched by the CPU without first fetching the
first word of the instruction. This is important when a two-word instruction is skipped by a
skip instruction (see Figure 2-15).
Figure 2-18: Instruction Pipeline Flow – 2-Word, 2-Cycle
7. Address Register Dependencies:
These are instructions that are subjected to a stall due to a data address dependency
between the X-data space read and write operations. An additional cycle is inserted
to resolve the resource conflict as discussed in Section 2.10 “Address Register Depen-
dencies”.
Figure 2-19: Instruction Pipeline Flow – 1-Word, 1-Cycle (With Instruction Stall)
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOV #0x1234,W0 Fetch 1 Execute 1
2. TBLRDL.w [W0++],W1 Fetch 2 Execute 2
3. MOV #0x00AA,W1 Fetch 3 PM Data
Read Cycle
Bus Read Execute 3
4. MOV #0x00CC,W0 Fetch 4 Execute 4
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOV #0xAA55,W0 Fetch 1 Execute 1
2. GOTO LABEL Fetch 2L Update PC
Fetch 2H
Forced NOP
3. LABEL: MOV W0,W2 Fetch 3 Execute 3
4. BSET PORTA, #3 Fetch 4 Execute 4
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOV W0,W1 Fetch 1 Execute 1
2. MOV [W1],[W4] Fetch 2 Execute 1
Stall Execute 2
3. MOV W2,W1 Fetch 3 Execute 3
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