Microchip Technology dsPIC30F - Page 499

© 2004 Microchip Technology Inc. DS70067C-page 20-9
Section 20. Serial Peripheral Interface (SPI)
Serial Peripheral
Interface (SPI)
20
Figure 20-3: SPI Master Mode Operation
SCKx
(CKP = 0
SCKx
(CKP = 1
SCKx
(CKP = 0
SCKx
(CKP = 1
4 Clock
modes
Input
Sample
Input
Sample
SDIx
bit7
bit0
SDOx bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7
bit0
SDIx
SPIxIF
(SMP = 1)
(SMP = 0)
(SMP = 1)
CKE = 1)
CKE = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
User writes
to SPIxBUF
SDOx
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
(CKE = 0)
(CKE = 1)
1 instruction cycle latency to set
SPIxIF flag bit
Note 1: Four SPI Clock modes shown to demonstrate CKP (SPIxCON<6>) and CKE (SPIxCON<8>) bit functionality only.
Only one of the four modes can be chosen for operation.
2: SDI and input sample shown for two different values of the SMP (SPIxCON<9>) bit, for demonstration purposes
only. Only one of the two configurations of the SMP bit can be chosen during operation.
3: If there are no pending transmissions, SPIxTXB is transferred to SPIxSR as soon as the user writes to SPIxBUF.
4: Operation for 8-bit mode shown. The 16-bit mode is similar.
SPIxSR moved
into SPIxRXB
User reads
SPIxBUF
(clock
output at
the SCKx
pin in
Master
mode)
(SPIxSTAT<0>)
SPITBF
SPIxTXB to SPIxSR
User writes new data
during transmission
SPIRBF
Two modes
available
for SMP
control
bit (see
Note 4)