dsPIC30F Family Reference Manual
DS70067C-page 20-10 © 2004 Microchip Technology Inc.
20.3.2.2 Slave Mode
The following steps should be taken to set up the SPI module for the Slave mode of operation:
1. Clear the SPIxBUF register.
2. If using interrupts:
• Clear the SPIxIF bit in the respective IFSn register.
• Set the SPIxIE bit in the respective IECn register.
• Write the SPIxIP bits in the respective IPCn register.
3. Write the desired settings to the SPIxCON register with MSTEN (SPIxCON<5>) = 0.
4. Clear the SMP bit.
5. If the CKE bit is set, then the SSEN bit must be set, thus enabling the SSx
pin.
6. Clear the SPIROV bit (SPIxSTAT<6>) and,
7. Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>).
In Slave mode, data is transmitted and received as the external clock pulses appear on the SCKx
pin. The CKP (SPIxCON<6>) and CKE (SPIxCON<8>) bits determine on which edge of the clock
data transmission occurs.
Both data to be transmitted and data that is received are respectively written into or read from
the SPIxBUF register.
The rest of the operation of the module is identical to that in the Master mode.
A few additional features provided in the Slave mode are:
Slave Select Synchronization: The SSx
pin allows a Synchronous Slave mode. If the SSEN
(SPIxCON<7>) bit is set, transmission and reception is enabled in Slave mode only if the SSx
pin is driven to a low state. The port output or other peripheral outputs must not be driven in order
to allow the SSx
pin to function as an input. If the SSEN bit is set and the SSx pin is driven high,
the SDOx pin is no longer driven and will tri-state even if the module is in the middle of a
transmission. An aborted transmission will be retried the next time the SSx
pin is driven low using
the data held in the SPIxTXB register. If the SSEN bit is not set, the SSx
pin does not affect the
module operation in Slave mode.
SPITBF Status Flag Operation: The function of the SPITBF (SPIxSTAT<1>) bit is different in
the Slave mode of operation. The following describes the function of the SPITBF for various
settings of the Slave mode of operation:
1. If SSEN (SPIxCON<7>) is cleared, the SPITBF is set when the SPIxBUF is loaded by the
user code. It is cleared when the module transfers SPIxTXB to SPIxSR. This is similar to
the SPITBF bit function in Master mode.
2. If SSEN (SPIxCON<7>) is set, the SPITBF is set when the SPIxBUF is loaded by the user
code. However, it is cleared only when the SPIx module completes data transmission. A
transmission will be aborted when the SSx
pin goes high and may be retried at a later
time. Each data word is held in SPIxTXB until all bits are transmitted to the receiver.
Note: To meet module timing requirements, the SSx pin must be enabled in Slave mode
when CKE = 1. (Refer to Figure 20-6 for details.)
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