© 2004 Microchip Technology Inc. DS70067C-page 20-15
Section 20. Serial Peripheral Interface (SPI)
Serial Peripheral
Interface (SPI)
20
Figure 20-7: SPI Master, Frame Master Connection Diagram
20.3.5.1 SCKx in Framed SPI Modes
When FRMEN (SPIxCON<14>) = 1 and MSTEN (SPIxCON<5>) = 1, the SCKx pin becomes an
output and the SPI clock at SCKx becomes a free running clock.
When FRMEN = 1 and MSTEN = 0, the SCKx pin becomes an input. The source clock provided
to the SCKx pin is assumed to be a free running clock.
The polarity of the clock is selected by the CKP (SPIxCON<6>) bit. The CKE (SPIxCON<8>) bit
is not used for the Framed SPI modes and should be programmed to ‘0’ by the user software.
When CKP = 0, the frame sync pulse output and the SDOx data output change on the rising edge
of the clock pulses at the SCKx pin. Input data is sampled at the SDIx input pin on the falling edge
of the serial clock.
When CKP = 1, the frame sync pulse output and the SDOx data output change on the falling
edge of the clock pulses at the SCKx pin. Input data is sampled at the SDIx input pin on the rising
edge of the serial clock.
Serial Receive Buffer
(SPIxRXB)
Shift Register
(SPIxSR)
MSbit
LSbit
SDOx
SDIx
dsPIC30F [SPI Master, Frame Master]
Serial Receive Buffer
(SPIxRXB)
Shift Register
(SPIxSR)
LSbit
MSbit
SDIx
SDOx
PROCESSOR 2
Serial Clock
Note 1: In Framed SPI modes, the SSx pin is used to transmit/receive the frame synchronization pulse.
2: Framed SPI modes require the use of all four pins (i.e., using the SSx
pin is not optional).
3: The SPIxTXB and SPIxRXB registers are memory mapped to the SPIxBUF register.
SCKx
SSx
SSx
SCKx
Serial Transmit Buffer
(SPIxTXB)
Serial Transmit Buffer
(SPIxTXB)
Frame Sync.
Pulse
SPI Buffer
(SPIxBUF)
SPI Buffer
(SPIxBUF)
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