dsPIC30F Family Reference Manual
DS70067C-page 20-16 © 2004 Microchip Technology Inc.
20.3.5.2 SPIx Buffers in Framed SPI Modes
When SPIFSD (SPIxCON<13>) = 0, the SPIx module is in the Frame Master mode of operation.
In this mode, the frame sync pulse is initiated by the module when the user software writes the
transmit data to SPIxBUF location (thus writing the SPIxTXB register with transmit data). At
the end of the frame sync pulse, the SPIxTXB is transferred to the SPIxSR and data
transmission/reception begins.
When SPIFSD (SPIxCON<13>) = 1, the module is in Frame Slave mode. In this mode, the frame
sync pulse is generated by an external source. When the module samples the frame sync pulse,
it will transfer the contents of the SPIxTXB register to the SPIxSR and data transmission/
reception begins. The user must make sure that the correct data is loaded into the SPIxBUF for
transmission before the frame sync pulse is received.
20.3.5.3 SPI Master Mode and Frame Master Mode
This Framed SPI mode is enabled by setting the MSTEN (SPIxCON<5>) and FRMEN
(SPIxCON<14>) bits to ‘1’ and the SPIFSD (SPIxCON<13>) bit to ‘0’. In this mode, the serial
clock will be output continuously at the SCKx pin, regardless of whether the module is
transmitting. When the SPIxBUF is written, the SSx
pin will be driven high on the next transmit
edge of the SCKx clock. The SSx
pin will be high for one SCKx clock cycle. The module will start
transmitting data on the next transmit edge of the SCKx, as shown in Figure 20-8. A connection
diagram indicating signal directions for this Operating mode is shown in Figure 20-7.
Figure 20-8: SPI Master, Frame Master
Note: Receiving a frame sync pulse will start a transmission, regardless of whether data
was written to SPIxBUF. If no write was performed, the old contents of SPIxTXB will
be transmitted.
SCKx
SSx
SDOx
(CKP = 0)
Bit 15 Bit 14 Bit 13 Bit 12
SDIx
Bit 15
Bit 14
Bit 13
Bit 12
Write to SPIxBUF
Receive Samples at SDIx
Pulse generated at SSx
SCKx
(CKP = 1)
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