© 2004 Microchip Technology Inc. DS70067C-page 20-17
Section 20. Serial Peripheral Interface (SPI)
Serial Peripheral
Interface (SPI)
20
20.3.5.4 SPI Master Mode and Frame Slave Mode
This Framed SPI mode is enabled by setting the MSTEN, FRMEN and the SPIFSD bits to ‘1’.
The SSx
pin is an input, and it is sampled on the sample edge of the SPI clock. When it is
sampled high, data will be transmitted on the subsequent transmit edge of the SPI clock, as
shown in Figure 20-9. The interrupt flag, SPIxIF, is set when the transmission is complete. The
user must make sure that the correct data is loaded into the SPIxBUF for transmission before the
signal is received at the SSx
pin. A connection diagram indicating signal directions for this
Operating mode is shown in Figure 20-10.
Figure 20-9: SPI Master, Frame Slave
Figure 20-10: SPI Master, Frame Slave Connection Diagram
SCK
FSYNC
SDO
(CKP = 0)
Bit 15 Bit 14 Bit 13 Bit 12
SDI
Sample SSx pin
for frame sync. pulse
Receive Samples at SDIx
Bit 15
Bit 14
Bit 13
Bit 12
Write to
SPIxBUF
SCKx
(CKP = 1)
SDOx
SDIx
dsPIC30F
Serial Clock
Note 1: In Framed SPI modes, the SSx
pin is used to transmit/receive the frame synchronization
pulse.
2: Framed SPI modes require the use of all four pins (i.e., Using the SSx
pin is not optional).
SSx
SCKx
Frame Sync.
Pulse
SDIx
SDOx
PROCESSOR 2
SSx
SCKx
[SPI Master, Frame Slave]
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