dsPIC30F Family Reference Manual
DS70067C-page 20-18 © 2004 Microchip Technology Inc.
20.3.5.5 SPI Slave Mode and Frame Master Mode
This framed SPI mode is enabled by setting the MSTEN (SPIxCON<5>) bit to ‘0’, the FRMEN
(SPIxCON<14>) bit to ‘1’ and the SPIFSD (SPIxCON<13>) bit to ‘0’. The input SPI clock will be
continuous in Slave mode. The SSx
pin will be an output when the SPIFSD bit is low. Therefore,
when the SPIBUF is written, the module will drive the SSx
pin high on the next transmit edge of
the SPI clock. The SSx
pin will be driven high for one SPI clock cycle. Data will start transmitting
on the next SPI clock transmit edge. A connection diagram indicating signal directions for this
Operating mode is shown in Figure 20-11.
Figure 20-11: SPI Slave, Frame Master Connection Diagram
20.3.5.6 SPI Slave Mode and Frame Slave Mode
This Framed SPI mode is enabled by setting the MSTEN (SPIxCON<5>) bit to ‘0’, the FRMEN
bit (SPIxCON<14>) to ‘1’ and the SPIFSD (SPIxCON<13>) bit to ‘1’. Therefore, both the SCKx
and SSx
pins will be inputs. The SSx pin will be sampled on the sample edge of the SPI clock.
When SSx
is sampled high, data will be transmitted on the next transmit edge of SCKx. A
connection diagram indicating signal directions for this Operating mode is shown in Figure 20-12.
Figure 20-12: SPI Slave, Frame Slave Connection Diagram
SDOx
SDIx
dsPIC30F
Serial Clock
Note 1: In Framed SPI modes, the SSx
pin is used to transmit/receive the frame synchronization
pulse.
2: Framed SPI modes require the use of all four pins (i.e., Using the SSx
pin is not optional).
SSx
SCKx
Frame Sync.
Pulse
SDIx
SDOx
PROCESSOR 2
SSx
SCKx
[SPI Slave, Frame Slave]
SDOx
SDIx
dsPIC30F
Serial Clock
Note 1: In Framed SPI modes, the SSx
pin is used to transmit/receive the frame synchronization
pulse.
2: Framed SPI modes require the use of all four pins (i.e., Using the SSx
pin is not optional).
SSx
SCKx
Frame Sync.
Pulse
SDIx
SDOx
PROCESSOR 2
SSx
SCKx
[SPI Master, Frame Slave]
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