© 2004 Microchip Technology Inc. DS70049C-page 2-37
Section 2. CPU
CPU
2
If a RAW data dependency is detected, the dsPIC30F will begin an instruction stall. During an
instruction stall, the following events occur:
1. The write operation underway (for the previous instruction) is allowed to complete as normal.
2. Data space is not addressed until after the instruction stall.
3. PC increment is inhibited until after the instruction stall.
4. Further instruction fetches are inhibited until after the instruction stall.
2.10.2.1 Instruction Stall Cycles and Interrupts
When an interrupt event coincides with two adjacent instructions that will cause an instruction
stall, one of two possible outcomes could occur:
1. The interrupt could be coincident with the first instruction. In this situation, the first instruc-
tion will be allowed to complete and the second instruction will be executed after the ISR
completes. In this case, the stall cycle is eliminated from the second instruction because
the exception process provides time for the first instruction to complete the write phase.
2. The interrupt could be coincident with the second instruction. In this situation, the second
instruction and the appended stall cycle will be allowed to execute prior to the ISR. In this
case, the stall cycle associated with the second instruction executes normally. However,
the stall cycle will be effectively absorbed into the exception process timing. The exception
process proceeds as if an ordinary two-cycle instruction was interrupted.
2.10.2.2 Instruction Stall Cycles and Flow Change Instructions
The CALL and RCALL instructions write to the stack using W15 and may, therefore, force an
instruction stall prior to the next instruction, if the source read of the next instruction uses W15.
The RETFIE and RETURN instructions can never force an instruction stall prior to the next
instruction because they only perform read operations. However, the user should note that the
RETLW instruction could force a stall, because it writes to a W register during the last cycle.
The GOTO and branch instructions can never force an instruction stall because they do not
perform write operations.
2.10.2.3 Instruction Stalls and DO and REPEAT Loops
Other than the addition of instruction stall cycles, RAW data dependencies will not affect the
operation of either DO or REPEAT loops.
The pre-fetched instruction within a REPEAT loop does not change until the loop is complete or
an exception occurs. Although register dependency checks occur across instruction boundaries,
the dsPIC30F effectively compares the source and destination of the same instruction during a
REPEAT loop.
The last instruction of a DO loop either pre-fetches the instruction at the loop start address or the
next instruction (outside the loop). The instruction stall decision will be based on the last
instruction in the loop and the contents of the pre-fetched instruction.
2.10.2.4 Instruction Stalls and Program Space Visibility (PSV)
When program space (PS) is mapped to data space by enabling the PSV (CORCON<2>) bit, and
the X space EA falls within the visible program space window, the read or write cycle is redirected
to the address in program space. Accessing data from program space takes up to 3 instruction
cycles.
Instructions operating in PSV address space are subject to RAW data dependencies and
consequent instruction stalls, just like any other instruction.
Consider the following code segment:
ADD W0,[W1],[W2++] ; PSV = 1, W1=0x8000, PSVPAG=0xAA
MOV [W2],[W3]
This sequence of instructions would take 5 instruction cycles to execute. 2 instruction cycles are
added to perform the PSV access via W1. Furthermore, an instruction stall cycle is inserted to
resolve the RAW data dependency caused by W2.
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