dsPIC30F Family Reference Manual
DS70070B-page 23-48 © 2004 Microchip Technology Inc.
23.6.6.3 Receive Error Interrupts
A receive error interrupt will be indicated by the ERRIF bit (CiINTF<5>). This bit shows that an
error condition occurred. The source of the error can be determined by checking the bits in the
CAN Interrupt Status Register CiINTF. The bits in this register are related to receive and transmit
errors. The following subsequences will show which flags are linked to the receive errors.
23.6.6.3.1 Invalid Message Received Interrupt
If any type of error occurred during reception of the last message, an error will be indicated by
the IVRIF bit (CiINTF<7>). The specific error that occurred is unknown. This bit can be used
(optionally with an interrupt) for autobaud detection with the device in Listen Only mode. This
error is not an indicator that any action needs to be taken, but an indicator that an error has
occurred on the CAN bus.
23.6.6.3.2 Receiver Overrun Interrupt
The RXnOVR bit (CiINTF<15>, CiINTF<14>) indicates that an overrun condition occurred for the
receive buffer. An overrun condition occurs when the Message Assembly Buffer (MAB) has
assembled a valid received message, the message is accepted through the acceptance filters,
however, the receive buffer associated with the filter is not clear of the previous message. The
overflow error interrupt will be set and the message is discarded. While in the overrun situation,
the module will stay synchronized with the CAN bus and is able to transmit and receive
messages.
23.6.6.4 Receiver Warning Interrupt
The RXWAR bit (CiINTF<8>) indicates that the Receive Error Counter has reached the CPU
warning limit of 96. When RXWAR transitions from a ‘0’ to a ‘1’, it will cause the Error Interrupt
Flag ERRIF to become set. This bit cannot be manually cleared, as it should remain an indicator
that the Receive Error Counter has reached the CPU warning limit of 96. The RXWAR bit will
become clear automatically if the Receive Error Counter becomes less than or equal to 95. The
ERRIF bit can be manually cleared allowing the interrupt service routine to be exited without
affecting the RXWAR bit.
23.6.6.5 Receiver Error Passive
The RXEP bit (CiINTF<11>) indicates that the Receive Error Counter has exceeded the Error
Passive limit of 127 and the module has gone to Error Passive state. When the RXEP bit transi-
tions from a ‘0’ to a ‘1’, it will cause the error interrupt flag to become set. The RXEP bit cannot
be manually cleared, as it should remain an indicator that the bus is in Error State Passive. The
RXEP bit will become clear automatically if the Receive Error Counter becomes less than or
equal to 127. The ERRIF bit can be manually cleared allowing the interrupt service routine to be
exited without affecting the RXEP bit.
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