Microchip Technology dsPIC30F - Page 651

© 2004 Microchip Technology Inc. DS70070B-page 23-53
Section 23. CAN
CAN Module
23
Figure 23-16: Loss of Arbitration During Transmission
1 2
4
5
- Processor sets TXREQ while module inactive. TXLARB bit cleared.
- Module in inactive state. Module begins transmission of queued message.
- Module waits for 11 recessive bits before re-trying transmission of queued message.
- At successful completion of transmission, TXREQ bit cleared and TXnIF bit set.
CAN bus
3
TXREQ
- Message loses arbitration. Module releases bus and sets TXLARB bit.
CiTX
TXnIF
TXLARB
1
2
3
4
5