© 2004 Microchip Technology Inc. DS70074C-page 26-9
Section 26. Appendix
Appendix
26
A.4.2 Clock Synchronization
Clock synchronization occurs after the devices have started arbitration. This is performed using
a wired-AND connection to the SCL line. A high-to-low transition on the SCL line causes the
concerned devices to start counting off their low period. Once a device clock has gone low, it will
hold the SCL line low until its SCL high state is reached. The low-to-high transition of this clock
may not change the state of the SCL line if another device clock is still within its low period. The
SCL line is held low by the device with the longest low period. Devices with shorter low periods
enter a high wait-state until the SCL line comes high. When the SCL line comes high, all
devices start counting off their high periods. The first device to complete its high period will pull
the SCL line low. The SCL line high time is determined by the device with the shortest high
period, Figure A-10.
Figure A-10: Clock Synchronization
CLK 1
CLK 2
SCL
Wait
State
Start Counting
High Period
Counter
Reset
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