Microchip Technology dsPIC30F - Page 90

dsPIC30F Family Reference Manual
DS70051C-page 4-6 © 2004 Microchip Technology Inc.
4.3.2 Table Address Generation
For all table instructions, a W register address value is concatenated with the 8-bit Data Table
Page register, TBLPAG, to form a 23-bit effective program space address plus a byte select bit,
as shown in Figure 4-4. As there are 15 bits of program space address provided from the
W register, the data table page size in program memory is, therefore, 32K words.
Figure 4-4: Address Generation for Table Operations
4.3.3 Program Memory Low Word Access
The TBLRDL and TBLWTL instructions are used to access the lower 16 bits of program memory
data. The LSb of the W register address is ignored for word-wide table accesses. For byte-wide
accesses, the LSb of the W register address determines which byte is read. Figure 4-5
demonstrates the program memory data regions accessed by the TBLRDL and TBLWTL
instructions.
Figure 4-5: Program Data Table Access (LSWord)
TBLPAG
8 bits from TBLPAG
EA
EA<0> Selects Byte
24-bit EA
TBLPAG<7> Selects
User/Configuration
Space
01507
16 bits from Wn
0
8
16
PC Address
0x000100
0x000102
0x000104
0x000106
23
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(Read a
s ‘0’)
TBLRDL.W
TBLRDL.B (Wn<0> = 1 )
TBLRDL.B (Wn<0> = 0 )