NEC UNIVERGE SV8500 - Page 685

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CHAPTER 5 Operation Procedure for System with PIR
The following figures show a block diagram of the CPU controlling block, where CPU 0 is active.
Figure 5-17 CPU Controlling Block Diagram (1-IMG)
Local I/O BUS
TSW
EXB INT
MUX INT
MUX
BUS0 BUS1
Local I/O BUS
TSW
MUX
PM Bus
LC/TRK LC/TRK
PIR0
PIR1
PIR2
PIR3
PM Bus
LC/TRK LC/TRK
MUX
MUX
PM Bus
LC/TRK LC/TRK
MUX
MUX
PM Bus
LC/TRK LC/TRK
MUX
MUX
MUX : PH-PC36
TSW : PH-SW10-A, etc.
: Circuit Card
: CPU Controlling Route
: Signal
: Cable
SV8500 Server
EXB0
EMA
IOC
(option)
IOC
(option
EXB1
CPU0 CPU1
PCI-Ex Bus
(PCI Express)
PCI-Ex Bus
(PCI Express)
EXB INT
MUX INT