NEC UNIVERGE SV8500 - Page 84

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CHAPTER 1 General
Figure 1-17 CPU Controlling Block Diagram (4-IMG)
Note 1:
Circuit cards shown in dotted line are in STBY mode.
Note 2: When the CPU ACT/STBY is changed over, GT will also be changed over in TSWR.
Note 3: IOC card is option.
[Symbols]
: CPU Controlling Routes : Cable
: Circuit Card (ACT) : Circuit Card (STBY)
: External Cable : Clock Oscillator
: Signal
LC/TRK
MUX
MUX
LC/TRK
PM BUS
PM BUS
LC/TRK
MUX
MUX
LC/TRK
PM BUS
PM BUS
LC/TRK
MUX
MUX
LC/TRK
PM BUS
PM BUS
LC/TRK
MUX
MUX
LC/TRK
PM BUS
PM BUS
IMG0
PIR 3
PIR 2
PIR 1
PIR 0
LC/TRK
MUX
MUX
LC/TRK
PM BUS
PM BUS
LC/TRK
MUX
MUX
LC/TRK
PM BUS
PM BUS
LC/TRK
MUX
MUX
LC/TRK
PM BUS
PM BUS
LC/TRK
MUX
MUX
LC/TRK
PM BUS
PM BUS
IMG1
PIR 3
PIR 2
PIR 1
PIR 0
GT :PH-GT09
TSW :PH-SW12
DLKC:PH-PC20
PLO :PH-CK16-D
MUX :PH-PC36
TSWR
TSW 00 TSW 10 TSW 11TSW 01
PLO 0 PLO 1
DLKC 1
DLKC 0
DLKC 1
GT 1
GT 0
DLKC BUS
DLKC BUS
Local I/O BUS
Local I/O BUS
DLKC BUS
DLKC BUS
TSW
02
TSW
03
TSW
13
TSW
12
To IMG 2To IMG 3 To IMG 3To IMG 2
BUS0
BUS1
MUX/INT MUX/INT MUX/INTMUX/INT
M
U
X
003
M
U
X
002
M
U
X
001
M
U
X
000
M
U
X
013
M
U
X
012
M
U
X
011
M
U
X
010
M
U
X
100
M
U
X
101
M
U
X
102
M
U
X
103
M
U
X
110
M
U
X
111
M
U
X
112
M
U
X
113
MUX
/INT
MUX
/INT
MUX
/INT
MUX
/INT
SV8500 Server
EXB0
EMA
IOC
(option)
IOC
(option)
EXB1
CPU Board 0 CPU Board 1
PCI-Ex bus (PCI Express)
PCI-Ex bus (PCI Express)
(Note 3)
BUS
Local I/O
BUS
Local I/O