R&S ESR Series

Remote Control
R&S
®
ESR
584User Manual 1175.7068.02 ─ 12
Bit No. Meaning
6 LMARgin 7 FAIL
This bit is set if limit margin 7 is violated.
7 LMARgin 8 FAIL
This bit is set if limit margin 8 is violated.
8 to 14 Not used
15 This bit is always 0.
STATus:QUEStionable:POWer Register
The STATus:QUEStionable:POWer register contains information about possible over-
load situations that may occur during operation of the R&S ESR.
You can read out the registers with STATus:QUEStionable:POWer:CONDition? or
STATus:QUEStionable:POWer[:EVENt]?.
Table 11-13: Meaning of the bits used in the STATus:QUEStionable:POWer register
Bit No. Meaning
0 OVERload
This bit is set if an overload occurs at the RF input.
The R&S ESR displays the enhancement label "OVLD".
1 UNDerload
This bit is set if an underload occurs at the RF input.
The R&S ESR displays the enhancement label "UNLD".
2 IF_OVerload
This bit is set if an overload occurs in the IF path.
The R&S ESR displays the enhancement label "IFOVL".
3 to 14 Unused
15 This bit is always 0.
STATus:QUEStionable:TRANsducer Register
The STATus:QUEStionable:TRANsducer register contains information about trans-
ducer breaks.
It indicates that a transducer break has been reached. It also indicates the next range
that is to be swept. You can continue the sweep with INITiate<n>:CONMeas.
You can read out the registers with STATus:QUEStionable:TRANsducer:
CONDition? or STATus:QUEStionable:TRANsducer[:EVENt]? on page 995.
Remote Control - Basics