RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 219 of 920
Dec 22, 2016
Figure 7 - 66 Example of Set Contents of Registers When PWM Function (Slave Channel) Is Used
(a) Timer mode register mp (TMRmp)
(b) Timer output register m (TOm)
(c) Timer output enable register m (TOEm)
(d) Timer output level register m (TOLm)
(e) Timer output mode register m (TOMm)
Note TMRm2: MASTERmp bit
TMRm1, TMRm3: SPLITmp bit
Remark m: Unit number (m = 0), n: Master channel number (n = 0, 2)
p: Slave channel number (p = 3)
1514131211109876543210
TMRmp
CKSmp1
1/0
CKSmp0
00
CCSmp
0
M/S
Note
0
STSmp2
1
STSmp1
0
STSmp0
0
CISmp1
0
CISmp0
000
MDmp3
1
MDmp2
0
MDmp1
0
MDmp0
1
Operation mode of channel p
100B: One-count mode
Start trigger during operation
1: Trigger input is valid.
Selection of TImp pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
100B: Selects INTTMmn of master channel.
Setting of MASTERmn bit (channel 2)
0: Slave channel
Setting of SPLITmp bit (channels 1, 3)
0: 16-bit timer mode
Count clock selection
0: Selects operation clock (f
MCK).
Operation clock (f
MCK) selection
00B: Selects CKm0 as operation clock of channel p.
10B: Selects CKm1 as operation clock of channel p.
* Make the same setting as master channel.
Bit p
TOm
TOmp
1/0
0: Outputs 0 from TOmp.
1: Outputs 1 from TOmp.
Bit p
TOEm
TOEmp
1/0
0: Stops the TOmp output operation by counting operation.
1: Enables the TOmp output operation by counting operation.
Bit p
TOLm
TOLmp
1/0
0: Positive logic output (active-high)
1: Negative logic output (active-low)
Bit p
TOMm
TOMmp
1
1: Sets the slave channel output mode.
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