RL78/G1H CHAPTER 13 A/D CONVERTER
R01UH0575EJ0120 Rev. 1.20 Page 293 of 920
Dec 22, 2016
Note 1. For the second and subsequent conversion in sequential conversion mode, the conversion start time and stabilization
wait time for A/D power supply do not occur after a hardware trigger is detected (see
Table 13 - 4).
Note 2. 1.8 V ≤ VDD ≤ 3.6 V
Note 3. 2.4 V ≤ VDD ≤ 3.6 V
Note 4. 2.7 V ≤ VDD ≤ 3.6 V
Note 5. These are the numbers of clock cycles when conversion is with 10-bit resolution. When eight-bit resolution is selected,
the values are shorter by two cycles of the conversion clock (f
AD).
Caution 1. The A/D conversion time must also be within the relevant range of conversion times (tCONV) described in 31.6.1
A/D converter characteristics.
Note that the conversion time (t
CONV) does not include the A/D power supply stabilization wait time.
Caution 2. Rewrite the FR2 to FR0, LV1 and LV0 bits to other than the same data while conversion is stopped (ADCS = 0,
ADCE = 0).
Caution 3. The above conversion time does not include conversion state time. Conversion state time add in the first
conversion. Select conversion time, taking clock frequency errors into consideration.
Caution 4. When hardware trigger wait mode, specify the conversion time, including the A/D power supply stabilization wait
time from the hardware trigger detection.
Remark
fCLK: CPU/peripheral hardware clock frequency
Table 13 - 6 A/D Conversion Time Selection (4/4)
(4) When there is A/D power supply stabilization wait time Low-voltage mode 1, 2
(hardware trigger wait mode
Note 1
)
A/D Converter Mode
Register 0 (ADM0)
Mode Conversion
Clock
(f
AD)
Number of
A/D Power
Supply
Stabilization
Wait Clock
Number of
Conversion
Clock
Note 5
A/D Power
Supply
Stabilization
Wait Time +
Conversion
Time
A/D Power Supply Stabilization Wait Time
+ Conversion Time at 10-Bit Resolution
1.8 V
≤ VDD ≤ 3.6 V Note 2 Note 3 Note 4
FR
2
FR
1
FR
0
LV
1
LV
0
fCLK =
1 MHz
fCLK =
4 MHz
fCLK =
8 MHz
fCLK =
16 MHz
fCLK =
32 MHz
00010 Low-
voltage1
f
CLK/64 2 fAD 19 fAD
(number of
sampling
clock:
7 f
AD)
1344/f
CLK Setting
prohibited
Setting
prohibited
Setting
prohibited
84 μs42 μs
001 f
CLK/32 672/fCLK 84 μs 42 μs21 μs
010 f
CLK/16 336/fCLK 84 μs 42 μs 21 μs10.5 μs
011 f
CLK/8 168/fCLK 42 μs 21 μs 10.5 μs 5.25 μs
100 f
CLK/6 126/fCLK 31.25 μs 15.75 μs 7.875 μs 3.9375 μs
101 f
CLK/5 105/fCLK 105 μs 26.25 μs 13.125 μs 6.5625 μs 3.238125
μs
110 f
CLK/4 84/fCLK 84 μs21 μs 10.5 μs5.25 μs 2.625 μs
111 f
CLK/2 42/fCLK 42 μs 10.5 μs5.25 μs 2.625 μsSetting
prohibited
00011 Low-
voltage2
f
CLK/64 2 fAD 17 fAD
(number of
sampling
clock:
5 f
AD)
1216/f
CLK Setting
prohibited
Setting
prohibited
Setting
prohibited
76 μs38 μs
001 f
CLK/32 608/fCLK 76 μs 38 μs19 μs
010 f
CLK/16 304/fCLK 76 μs 38 μs 19 μs9.5 μs
011 f
CLK/8 152/fCLK 38 μs 19 μs9.5 μs 4.75 μs
100 f
CLK/6 114/fCLK 28.5 μs 14.25 μs 7.125 μs 3.5625 μs
101 f
CLK/5 95/fCLK 96 μs 23.75 μs 11.875 μs 5.938 μs 2.9688 μs
110 f
CLK/4 76/fCLK 76 μs19 μs9.5 μs4.75 μs 2.375 μs
111 f
CLK/2 38/fCLK 38 μs9.5 μs4.75 μs 2.375 μsSetting
prohibited
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