Renesas RL78/G1H - Page 497

RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA
R01UH0575EJ0120 Rev. 1.20 Page 479 of 920
Dec 22, 2016
(1) Master device operation
(a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception)
(i) When WTIMn = 0
(ii) When WTIMn = 1
Remark n = 0, 1
ST AD6 to AD0 D7 to D0R/W ACK ACK SPD7 to D0 ACK
SPTn = 1
↓
5
1 2 3 4
▲1: IICSn = 1000×110B
▲2: IICSn = 1000×000B
▲3: IICSn = 1000×000B (Sets the WTIMn bit to 1)
Note
▲4: IICSn = 1000××00B (Sets the SPTn bit to 1)
5: IICSn = 00000001B
Note To generate a stop condition, set the WTIMn bit to 1 and change the timing for generating the INTIICAn interrupt
request signal.
Remark ▲: Always generated
: Generated only when SPIEn = 1
× : Don’t care
ST AD6 to AD0 D7 to D0R/W ACK ACK SPD7 to D0 ACK
SPTn = 1
↓
4
3 2 1
▲1: IICSn = 1000×110B
▲2: IICSn = 1000×100B
▲3: IICSn = 1000××00B (Sets the SPTn bit to 1)
4: IICSn = 00000001B
Remark ▲: Always generated
: Generated only when SPIEn = 1
× : Don’t care