RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA
R01UH0575EJ0120 Rev. 1.20 Page 480 of 920
Dec 22, 2016
(b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart)
(i) When WTIMn = 0
(ii) When WTIMn = 1
Remark n = 0, 1
ST AD6 to AD0 D7 to D0R/W ACK ACK
STTn = 1
↓
SPST AD6 to AD0 D7 to D0R/W ACK ACK
SPTn = 1
↓
7
6 5 4 3 2 1
▲1: IICSn = 1000×110B
▲2: IICSn = 1000×000B (Sets the WTIMn bit to 1)
Note 1
▲3: IICSn = 1000××00B (Clears the WTIMn bit to 0
Note 2
, sets the STTn bit to 1)
▲4: IICSn = 1000×110B
▲5: IICSn = 1000×000B (Sets the WTIMn bit to 1)
Note 3
▲6: IICSn = 1000××00B (Sets the SPTn bit to 1)
7: IICSn = 00000001B
Note 1. To generate a start condition, set the WTIMn bit to 1 and change the timing for generating the INTIICAn interrupt
request signal.
Note 2. Clear the WTIMn bit to 0 to restore the original setting.
Note 3. To generate a stop condition, set the WTIMn bit to 1 and change the timing for generating the INTIICAn interrupt
request signal.
Remark ▲: Always generated
: Generated only when SPIEn = 1
× : Don’t care
ST AD6 to AD0 D7 to D0R/W ACK ACK
STTn = 1
↓
SPST AD6 to AD0 D7 to D0R/W ACK ACK
SPTn = 1
↓
5
4 3 2 1
▲1: IICSn = 1000×110B
▲2: IICSn = 1000××00B (Sets the STTn bit to 1)
▲3: IICSn = 1000×110B
▲4: IICSn = 1000××00B (Sets the SPTn bit to 1)
5: IICSn = 00000001B
Remark ▲: Always generated
: Generated only when SPIEn = 1
× : Don’t care
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