RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS
R01UH0575EJ0120 Rev. 1.20 Page 707 of 920
Dec 22, 2016
Table 19 - 2 Interrupt Source List (2/2)
Note 1. The default priority determines the sequence of interrupts if two or more maskable interrupts occur simultaneously.
Zero indicates the highest priority and 44 indicates the lowest priority.
Note 2. Basic configuration types (A) to (C) correspond to (A) to (C) in Figure 19 - 1.
Note 3. Be used at the flash self-programming library or the data flash library.
Note 4. When bit 7 (LVIMD) of the voltage detection level register (LVIS) is set to 1.
Note 5. When the instruction code in FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator.
Interrupt Type
Default Priority
Note 1
Interrupt Source
Internal/External
Vector Table Address
Basic Configuration Type
Note 2
Name Trigger
Maskable
29 INTTM10 End of timer channel 10 count or capture
Internal
0042H (A)
30 INTTM11 End of timer channel 11 count or capture 0044H
31 INTTM12 End of timer channel 12 count or capture 0046H
32 INTTM13 End of timer channel 13 count or capture 0048H
33 INTP6 Pin input edge detection
External
004AH (B)
34 INTP7 004CH
35 INTP8 004EH
36 INTP9 0050H
37 INTP10 0052H
38 INTP11 0054H
42
INTSRE3 UART3 reception communication error occurrence
Internal
005CH
(A)
INTTM13H
End of timer channel 13 count or capture
(at 8-bit timer operation)
43 INTIICA1 End of IICA1 communication 0060H
44
INTFL
Reserved
Note 3
0062H
Software
—
BRK Execution of BRK instruction — 007EH (C)
Reset
—
RESET
RESET
pin input
— 0000H —
POR Power-on-reset
LVD
Voltage detection
Note 4
WDT Overflow of watchdog timer
TRAP
Execution of illegal instruction
Note 5
IAW Illegal-memory access
RPE RAM parity error
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