Renesas RL78/G1H - Page 74

RL78/G1H CHAPTER 4 CPU ARCHITECTURE
R01UH0575EJ0120 Rev. 1.20 Page 56 of 920
Dec 22, 2016
Note The value of this register is 00H if the AMPM bit (bit 3 of real-time clock control register 0 (RTCC0)) is set to 1 after reset.
Table 4 - 7 Special Function Register (SFR) List (3/5)
Address
Special Function Register (SFR)
Name
Symbol R/W
Manipulable Bit Range
After Reset
1-bit 8-bit 16-bit
FFF72H Timer data register 11 TDR11L TDR11 R/W —
√√00H
FFF73H TDR11H —
√ 00H
FFF74H Timer data register 12 TDR12 R/W — —
√ 0000H
FFF75H
FFF76H Timer data register 13 TDR13L TDR13 R/W —
√√00H
FFF77H TDR13H —
√ 00H
FFF90H 12-bit interval timer control register ITMC R/W — —
√ 0FFFH
FFF91H
FFF92H Second count register SEC R/W —
√ —00H
FFF93H Minute count register MIN R/W —
√ —00H
FFF94H
Hour count register HOUR
R/W —
√ —
12H
Note
FFF95H Week count register WEEK R/W — √ —00H
FFF96H Day count register DAY R/W —
√ —01H
FFF97H Month count register MONTH R/W —
√ —01H
FFF98H Year count register YEAR R/W —
√ —00H
FFF99H Watch error correction register SUBCUD R/W —
√ —00H
FFF9AH Alarm minute register ALARMWM R/W —
√ —00H
FFF9BH Alarm hour register ALARMWH R/W —
√ —12H
FFF9CH Alarm week register ALARMWW R/W —
√ —00H
FFF9DH Real-time clock control register 0 RTCC0 R/W
√√—00H
FFF9EH Real-time clock control register 1 RTCC1 R/W
√√—00H
FFFA0H Clock operation mode control register CMC R/W —
√ —00H
FFFA1H Clock operation status control
register
CSC
R/W
√√—C0H
FFFA2H Oscillation stabilization time counter
status register
OSTC
R
√√—00H
FFFA3H Oscillation stabilization time select
register
OSTS
R/W
—
√ —07H
FFFA4H System clock control register CKC R/W
√√—00H
FFFA5H Clock output select register 0 CKS0 R/W
√√—00H
FFFA6H Clock output select register 1 CKS1 R/W
√√—00H