Renesas RL78/G1H

RL78/G1H CHAPTER 4 CPU ARCHITECTURE
R01UH0575EJ0120 Rev. 1.20 Page 65 of 920
Dec 22, 2016
Table 4 - 15 Extended Special Function Register (2nd SFR) List (6/7)
Address
Extended Special Function Register
(2nd SFR) Name
Symbol R/W
Manipulable Bit Range
After Reset
1-bit 8-bit 16-bit
F01E6H Timer status register 13 TSR13L TSR13 R/W —
√√0000H
F01E7H — — —
F01F0H Timer channel enable status register
1
TE1L TE1 R/W —
√√0000H
F01F1H — — —
F01F2H Timer channel start register 1 TS1L TS1 R/W —
√√0000H
F01F3H — — —
F01F4H Timer channel stop register 1 TT1L TT1 R/W —
√√0000H
F01F5H — — —
F01F6H Timer clock select register 1 TPS1 R/W
——
√ 0000H
F01F7H
F01F8H Timer output register 1 TO1L TO1 R/W —
√√0000H
F01F9H — — —
F01FAH Timer output enable register 1 TOE1L TOE1 R/W —
√√0000H
F01FBH — — —
F01FCH Timer output level register 1 TOL1L TOL1 R/W —
√√0000H
F01FDH — — —
F01FEH Timer output mode register 1 TOM1L TOM1 R/W —
√√0000H
F01FFH — — —
F0230H IICA control register 00 IICCTL00 R/W
√√—00H
F0231H IICA control register 01 IICCTL01 R/W
√√—00H
F0232H IICA low-level width setting register 0 IICWL0 R/W —
√ —FFH
F0233H IICA high-level width setting register 0 IICWH0 R/W —
√ —FFH
F0234H Slave address register 0 SVA0 R/W —
√ —00H
F0238H IICA control register 10 IICCTL10 R/W
√√—00H
F0239H IICA control register 11 IICCTL11 R/W
√√—00H
F023AH IICA low-level width setting register 1 IICWL1 R/W —
√ —FFH
F023BH IICA high-level width setting register 1 IICWH1 R/W —
√ —FFH
F023CH Slave address register 1 SVA1 R/W —
√ —00H
F0240H Timer RJ control register 0 TRJCR0 R/W —
√ —00H
F0242H Timer RJ mode register 0 TRJMR0 R/W
√√—00H
F02E0H DTC base address register DTCBAR R/W
√√—FDH
F02E8H DTC activation enable register 0 DTCEN0 R/W
√√—00H
F02E9H DTC activation enable register 1 DTCEN1 R/W
√√—00H
F02EAH DTC activation enable register 2 DTCEN2 R/W
√√—00H
F02EBH DTC activation enable register 3 DTCEN3 R/W
√√—00H
F02ECH DTC activation enable register 4 DTCEN4 R/W
√√—00H
F02F0H Flash memory CRC control register CRC0CTL R/W
√√—00H
F02F2H Flash memory CRC operation result
register
PGCRCL R/W — —
√ 0000H