Renesas RL78/G1H

RL78/G1H CHAPTER 30 INSTRUCTION SET
R01UH0575EJ0120 Rev. 1.20 Page 852 of 920
Dec 22, 2016
Note 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no
data is accessed
Note 2. Number of CPU clocks (f
CLK) when the code flash memory is accessed, or when the data flash memory is accessed by
an 8-bit instruction.
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the
internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Table 30 - 19 Operation List (15/18)
Instruction
Group
Mnemonic Operands Bytes
Clocks
Clocks
Flag
Note 1 Note 2
ZACCY
Bit
manipulate
XOR1 CY, A.bit
21—
CY
←
CY
∨
A.bit
×
CY, PSW.bit
31—
CY
←
CY
∨
PSW.bit
×
CY, saddr.bit
31—
CY
←
CY
∨
(saddr).bit
×
CY, sfr.bit
31—
CY
←
CY
∨
sfr.bit
×
CY, [HL].bit
214
CY
←
CY
∨
(HL).bit
×
CY, ES:[HL].bit
325
CY
←
CY
∨
(ES, HL).bit
×
SET1 A.bit
21—
A.bit
←
1
PSW.bit
34—
PSW.bit
←
1
×××
!addr16.bit
42—
(addr16).bit
←
1
ES:!addr16.bit
53—
(ES, addr16).bit
←
1
saddr.bit
32—
(saddr).bit
←
1
sfr.bit
32—
sfr.bit
←
1
[HL].bit
22—
(HL).bit
←
1
ES:[HL].bit
33—
(ES, HL).bit
←
1
CLR1 A.bit
21—
A.bit
←
0
PSW.bit
34—
PSW.bit
←
0
×××
!addr16.bit
42—
(addr16).bit
←
0
ES:!addr16.bit
53—
(ES, addr16).bit
←
0
saddr.bit
32—
(saddr.bit)
←
0
sfr.bit
32—
sfr.bit
←
0
[HL].bit
22—
(HL).bit
←
0
ES:[HL].bit
33—
(ES, HL).bit
←
0
SET1 CY
21—
CY
←
1
1
CLR1 CY
21—
CY
←
0
0
NOT1 CY
21—
CY
←
CY
×