Renesas RL78/G1H User Manual

RL78/G1H CHAPTER 30 INSTRUCTION SET
R01UH0575EJ0120 Rev. 1.20 Page 853 of 920
Dec 22, 2016
Note 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data
is accessed.
Note 2. Number of CPU clocks (f
CLK) when the code flash memory is accessed, or when the data flash memory is accessed by
an 8-bit instruction.
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the
internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Table 30 - 20 Operation List (16/18)
Instruction
Group
Mnemonic Operands Bytes
Clocks
Clocks
Flag
Note 1 Note 2
ZACCY
Call/return CALL rp 2 3 — (SP - 2)
←
(PC + 2)
S
, (SP - 3)
←
(PC + 2)
H
,
(SP - 4)
←
(PC + 2)
L
, PC
←
CS, rp,
SP
←
SP - 4
$!addr20 3 3 — (SP - 2)
←
(PC + 3)
S
, (SP - 3)
←
(PC + 3)
H
,
(SP - 4)
←
(PC + 3)
L
, PC
←
PC + 3 + jdisp16,
SP
←
SP - 4
!addr16 3 3 — (SP - 2)
←
(PC + 3)
S
, (SP - 3)
←
(PC + 3)
H
,
(SP - 4)
←
(PC + 3)
L
, PC
←
0000, addr16,
SP
←
SP - 4
!!addr20 4 3 — (SP - 2)
←
(PC + 4)
S
, (SP - 3)
←
(PC + 4)
H
,
(SP - 4)
←
(PC + 4)
L
, PC
←
addr20,
SP
←
SP - 4
CALLT [addr5] 2 5 — (SP - 2)
←
(PC + 2)
S
, (SP - 3)
←
(PC + 2)
H
,
(SP - 4)
←
(PC + 2)
L
, PC
S ←
0000,
PC
H ←
(0000, addr5 + 1),
PC
L ←
(0000, addr5),
SP
←
SP - 4
BRK — 2 5 — (SP - 1)
←
PSW, (SP - 2)
←
(PC + 2)
S
,
(SP - 3)
←
(PC + 2)
H
, (SP - 4)
←
(PC + 2)
L
,
PC
S ←
0000,
PC
H ←
(0007FH), PC
L ←
(0007EH),
SP
←
SP - 4, IE
←
0
RET — 1 6 — PC
L ←
(SP), PC
H ←
(SP + 1),
PC
S ←
(SP + 2), SP
←
SP + 4
RETI — 2 6 — PC
L ←
(SP), PC
H ←
(SP + 1),
PC
S ←
(SP + 2), PSW
←
(SP + 3),
SP
←
SP + 4
RRR
RETB — 2 6 — PC
L ←
(SP), PC
H ←
(SP + 1),
PC
S ←
(SP + 2), PSW
←
(SP + 3),
SP
←
SP + 4
RRR

Renesas RL78/G1H Specifications

General

Brand	Renesas
Model	RL78/G1H
Category	Microcontrollers
Language	English