RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS
R01UH0575EJ0120 Rev. 1.20 Page 878 of 920
Dec 22, 2016
Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4. C is the load capacitance of the SOp output lines.
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1.
p: CSI number (p = 10, 21, 30), m: Unit number (m = 0, 1), n: Channel number (n = 1, 2),
g: PIM and POM number (g = 0, 14)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 02, 11, 12))
CSI mode connection diagram (during communication at same potential)
Remark p: CSI number (p = 10, 21, 30)
(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(T
A = ‒40 to +85 °C, 1.8 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed main)
mode
LS (low-speed main) mode Unit
MIN. MAX. MIN. MAX.
SCKp cycle time t
KCY2 2.7 V ≤ VDD ≤ 3.6 V 16 MHz < fMCK 8/fMCK —ns
f
MCK ≤ 16 MHz 6/fMCK 6/fMCK ns
2.4 V
≤ VDD ≤ 3.6 V 6/fMCK
and 500
6/f
MCK
and 500
ns
1.8 V
≤ VDD ≤ 3.6 V 6/fMCK
and 750
6/f
MCK
and 750
ns
SCKp high-/
low-level width
t
KH2,
t
KL2
2.7 V ≤ VDD ≤ 3.6 V tKCY2/2 ‒ 8tKCY2/2 ‒ 8ns
1.8 V
≤ VDD ≤ 3.6 V tKCY2/2 ‒ 18 tKCY2/2 ‒ 18 ns
SIp setup time
(to SCKp↑)
Note 1
tSIK2 2.7 V ≤ VDD ≤ 3.6 V 1/fMCK + 20 1/fMCK + 30 ns
1.8 V
≤ VDD ≤ 3.6 V 1/fMCK + 30 1/fMCK + 30 ns
SIp hold time
(from SCKp↑)
Note 2
tKSI2 1.8 V ≤ VDD ≤ 3.6 V 1/fMCK + 31 1/fMCK + 31 ns
Delay time from
SCKp↓ to SOp
output
Note 3
tKSO2 2.7 V ≤ VDD ≤ 3.6 V
C = 30 pF
Note 4
2/fMCK + 44
2/f
MCK
+ 110
ns
2.4 V
≤ VDD ≤ 3.6 V 2/fMCK + 75
2/f
MCK
+ 110
ns
1.8 V
≤ VDD ≤ 3.6 V
2/f
MCK
+ 100 2/f
MCK
+ 110
ns
SCKp
SOp
User's device
SCK
SI
SIp SO
RL78 microcontroller
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