Renesas RL78/G1H User Manual

RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS
R01UH0575EJ0120 Rev. 1.20 Page 888 of 920
Dec 22, 2016
Note 1. Use it with VDD ≥ Vb.
Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and SCKp pin, and the N-ch open drain output (VDD tolerance) mode
for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For V
IH and
V
IL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
(7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock
input)
(T
A = ‒40 to +85 °C, 1.8 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed main)
mode
LS (low-speed main)
mode
Unit
MIN. MAX. MIN. MAX.
SCKp cycle time t
KCY2 2.7 V ≤ VDD < 3.6 V,
2.3 V
≤ Vb ≤ 2.7 V
24 MHz
< fMCK 20/fMCK —ns
20 MHz
< fMCK ≤ 24
MHz
16/fMCK —ns
16 MHz
< fMCK ≤ 20
MHz
14/fMCK —ns
8 MHz
< fMCK ≤ 16 MHz 12/fMCK —ns
4 MHz
< fMCK ≤ 8 MHz 8/fMCK 16/fMCK ns
f
MCK ≤ 4 MHz 6/fMCK 10/fMCK ns
1.8 V
≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Note 1
24 MHz < fMCK 48/fMCK —ns
20 MHz
< fMCK ≤ 24
MHz
36/fMCK —ns
16 MHz
< fMCK ≤ 20
MHz
32/fMCK —ns
8 MHz
< fMCK ≤ 16 MHz 26/fMCK —ns
4 MHz
< fMCK ≤ 8 MHz 16/fMCK 16/fMCK ns
f
MCK ≤ 4 MHz 10/fMCK 10/fMCK ns
SCKp high-/
low-level width
t
KH2,
t
KL2
2.7 V ≤ VDD < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V t KCY2 /2 ‒ 18 t KCY2 /2 ‒ 50 ns
1.8 V
≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
Note 1
t KCY2 /2 ‒ 50 t KCY2 /2 ‒ 50 ns
SIp setup time
(to SCKp↑)
Note 2
tSIK2 2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V 1/fMCK + 20 1/fMCK + 30 ns
1.8 V
≤ VDD ≤ 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
Note 1
1/fMCK + 30 1/fMCK + 30 ns
SIp hold time
(from SCKp↑)
Note 3
tKSI2 1/fMCK + 31 1/fMCK + 31 ns
Delay time from
SCKp
↓ to SOp
output
Note 4
tKSO2 2.7 V ≤ VDD < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2/f MCK + 214 2/f MCK + 573 ns
1.8 V
≤ VDD < 3.3 V, 1.8 V ≤ Vb ≤ 2.0 V
Note 1
,
Cb = 30 pF, Rv = 5.5 kΩ
2/f MCK + 573 2/f MCK + 573 ns

Renesas RL78/G1H Specifications

General

Brand	Renesas
Model	RL78/G1H
Category	Microcontrollers
Language	English