YOKOGAWA DL7440 User Manual

17-3
IM 701450-01E
17
Specifications
Item Specifications
Trigger type Edge: Activate the trigger on the edge of a single trigger source.
A->B(N): Trigger occurs n
th
time condition B becomes true after condition A becomes
true.
Count: 1 to 10
8
Condition A: Enter/Exit
Condition B: Enter/Exit
A Delay B: Trigger occurs first time condition B becomes true after specified delay
following condition A true.
Specified time: 3 ns to 5 s
Condition A: Enter/Exit
Condition B: Enter/Exit
OR: Trigger occurs on the OR logic of the trigger conditions set to multiple trigger
sources.
Trigger condition is edge or window. Rise (IN), Fall (Out), or Don’t Care can
be set to each channel CH1 to CH8/4
1
.
Pattern: Trigger occurs on the edge of the clock channel with respect to the True/False
condition of the parallel pattern set to multiple trigger sources. If the clock
channel is set to Don’t Care, trigger occurs on the Enter or Exit condition of
the True/False condition of the parallel pattern.
Parallel pattern is the AND of the channels.
Width: Trigger occurs on the True/False width of the parallel pattern of multiple trigger
sources.
Parallel pattern is the AND of the statuses of the channels or the AND of the
window conditions of the channels.
Pulse<Time: Trigger occurs when the width described
above is smaller than Time.
Pulse>Time: Trigger occurs when the width described
above is greater than Time.
T1<Pulse<T2: Trigger occurs when the width described
above is greater than T1 and smaller than
T2.
Time Out: Trigger occurs when the width described
exceeds Time.
Specified time: 1 ns to 1 s
Time accuracy
2
: ±(0.5% of the setting
4
+ 1 ns)
Minimum time detection width
2
:2 ns (typical value
5
)
TV: Activates a trigger on the video signal of various formats: NTSC, PAL,
SECAM, 1080/60i, 1080/50i, 720/60p, 480/60p, 1080/25p, 1080/24p, 1080/
24sF, and 1080/60p CH1 is the only input channel. Field number and line
number selectable.
Logic: Trigger occurs on the edge of the clock bit with respect to the True/False
condition of the parallel pattern of multiple logic inputs.
If the clock bit is set to Don’t Care, trigger occurs on the Enter or Exit condition
of the True/False condition of the parallel pattern.
Parallel pattern is the AND of the statuses of the bits of Pod A and B (16 bits)
Clock bit is an arbitrary bit of Pod A and B (16 bits).
• Condition A and Condition B are parallel patterns set using High, Low, and Don’t Care on
each channel CH1 to CH8/4
1
.
Trigger gate Trigger can be activated only when the trigger condition is met when the input from the
trigger gate input terminal (TRIG GATE IN) is active.
Active level can be set to high or low.
1 The maximum number of channels varies depending on the model.
2 Under standard operating conditions (see section 17.12) after the warm-up and calibration.
3 Under standard operating conditions (see section 17.12) after the warm-up.
4 The value of T2 for T1<Pulse<T2.
5 Typical value represents a typical or average value. It is not strictly warranted.
17.3 Trigger Section

YOKOGAWA DL7440 Specifications

General

Brand	YOKOGAWA
Model	DL7440
Category	Test Equipment
Language	English