TDM-CLK (TDM Bus Clock)
Issue 1 May 2002
8-1611555-233-143
System Technician-Demanded Tests:
Descriptions and Error Codes
Always investigate tests in the order presented in the table below when inspecting
errors in the system. For example, by clearing error codes associated with the
SAKI Reset test (#53), you may also clear errors generated from other tests in the
testing sequence.
Notes:
a. See ‘‘XXX-BD (Common Port Circuit Pack)’’ on page 8-1872 for
descriptions of these tests.
b. See ‘‘TONE-BD (Tone-Clock Circuit)’’ on page 8-1659 for a description of
this test.
c. See ‘‘TONE-PT (Tone Generator)’’ on page 8-1682 for descriptions of
these tests.
d. This test only runs on the standby IPSI or Tone-Clock circuit pack in a port
network with more than one IPSI or Tone-Clock circuit pack (high- or
critical-reliability option). The Tone-Clock circuit pack must be a TN780
code with firmware revision 2 or above, or be a TN2182.
e. Test #149 is not run on the TN2182.
Order of Investigation
Short Test
Sequence
Long Test
Sequence
Reset Board
Sequence D/ND
1
1. D = Destructive; ND = Nondestructive
SAKI Reset test (#53) (a) X D
Clock Health test (#46) (b) X X ND
Control Channel Loop-Around test (#52) (a) X X ND
Tone Generator Crosstalk test (#90) (c) X ND
Tone Generator Transmission test (#40) (c) X X ND
Tone Generator Audit/Update test (#41) (c) X X ND
TDM bus Clock Circuit Status Inquiry test
(#148)
XX ND
TDM bus Clock Slip Inquiry test (#149)(e) X X ND
TDM bus Clock PPM Inquiry test (#150) X X ND
TDM bus Clock Parameter Update test
(#151)
XX ND
Board Type Check test (#574) X X ND
Standby Reference Health Check test
(#651) (d)
XND
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