Intel Xeon User Manual

12 Design Guide
Tables
1-1 Reference Documents ........................................................................................15
1-2 Intel® Xeon™ Processor with 512 KB L2 Cache Feature Set Overview ............20
1-3 Platform Maximum Bandwidth Summary ............................................................23
3-1 Assumptions for System Placement Example ....................................................31
3-2 E7500 Chipset Customer Reference Board Requirements ................................33
4-1 CK408B Clock Groups........................................................................................35
4-2 Platform System Clock-Reference ......................................................................36
4-3 HOST_CLK[1:0]# Routing Guidelines.................................................................39
4-4 CLK66 Routing Guidelines..................................................................................42
4-5 CLK33_ICH3-S Routing Guidelines....................................................................45
4-6 CLK33 Routing Guidelines for PCI Device Down ...............................................46
4-7 CLK33 Routing Guidelines for PCI Slot ..............................................................47
4-8 CLK14 Routing Guidelines..................................................................................48
4-9 USBCLK Routing Guidelines ..............................................................................49
5-1 System Bus Signal Groups .................................................................................53
5-2 System Bus Routing Summary ...........................................................................55
5-3 2X and 4X Signal Groups....................................................................................56
5-4 Source Synchronous Signals with the Associated Strobes.................................56
5-5 AGTL+ Common Clock I/O Signals.....................................................................58
5-6 Asynchronous GTL+ and Miscellaneous Signals................................................59
5-7 BR[3:0]# Connection...........................................................................................64
6-1 DDR Channel Signal Groups ..............................................................................67
6-2 DQ/CB to DQS Mapping .....................................................................................70
6-3 Source Synchronous Signal Group Routing Guidelines .....................................71
6-4 Command Clock Pair Routing Guidelines...........................................................73
6-5 Source Clocked Signal Group Routing Guidelines .............................................75
6-6 Chip Select Routing Guidelines ..........................................................................76
6-7 Clock Enable Routing Guidelines........................................................................77
7-1 Hub Interface 2.0 Signal/Strobe Association.......................................................84
7-2 Hub Interface 2.0 Signal Groups.........................................................................84
7-3 Hub Interface 2.0 Routing Parameters................................................................84
7-4 Hub Interface 2.0 Reference Circuit Specifications.............................................87
7-5 Hub Interface 2.0 RCOMP Resistor Values........................................................88
7-6 Hub Interface 1.5 Signal Groups.........................................................................90
7-7 Hub Interface 1.5 Routing Parameters................................................................90
7-8 Hub Interface 1.5 Reference Circuit Specifications.............................................90
7-9 Hub Interface 1.5 RCOMP Resistor Values........................................................91
8-1 PCI/PCI-X Frequencies.......................................................................................93
8-2 Intel® P64H2 PCI/PCI-X Configuration Length Requirements ...........................94
8-3 Intel® P64H2 Hot Plug Configuration Length Requirements ..............................95
8-4 Hot Plug Clock Routing Length Parameters .......................................................96
8-5 No Hot Plug Clock Routing Length Parameters..................................................96
8-6 Loop Clock Configuration Routing Length Parameters.......................................97
8-7 SMBus Address Configuration............................................................................98
8-8 Hot Plug Mode ..................................................................................................103
8-9 Frequency Matrix ..............................................................................................104
8-10 Single Slot Parallel Mode Hot Plug Signal Table ..............................................105
8-11 Hot Plug Controller Output Signal Reset Values...............................................106

Intel Xeon Specifications

General

Brand	Intel
Model	Xeon
Category	Processor
Language	English