Intel Xeon User Manual

Design Guide 191
Schematic Checklist
SLP#
(CPUSLP#)
• Connect to both processors and ICH3-S.
Include 200
Ω ± 5% pull-up to VCC_CPU.
• Causes processor to enter sleep
state.
• Asynchronous GTL+ Input.
• Refer to Section 5.3.2.
SM_ALERT# • Should be connected to the SMBus
controller.
•SMBus I/O.
• Refer to Section 5.3.4.
SM_CLK
SM_DAT
• Connect to both processors and SMBus
controller.
• Recommend a pull-up resistor to VCC_3.3.
Resistor value is based on the number of
devices on the SMBus.
• SMBus Input.
• Refer to Section 5.3.4.
SM_EP_A[2:0] • Leave as no connect to set bit low, or pull-up
to SM_VCC through 100
Ω ± 5% resistor to
set bit high.
• Use these address bits to set a unique
SMBus address for the memory devices on
the processor. See the
Intel
®
Xeon™
Processor with 512 KB L2 Cache at 1.80
GHz, 2 GHz, and 2.20 GHz Datasheet
for
more details.
• Set the SMBus address for the
memory device on the processor.
These signals must be set at
power up with a unique address
per bus.
• These signals have 10 k
Ω pull-
downs on the processor
.
• SMBus Input.
• Refer to Section 5.3.4.
SM_TS_A[1:0] • Leave as no connect to set bit to high-
impedance state. Pull-up to SM_VCC
through 1 k
Ω ± 5% to set bit high. Pull-down
to VSS through 1 k
Ω ± 5% to set bit low. Use
these address bits to set a unique SMBus
address for the thermal devices on the
processor. See the
Intel
®
Xeon™ Processor
with 512 KB L2 Cache at 1.80 GHz, 2 GHz,
and 2.20 GHz Datasheet
for more details.
• These signals do not have internal
pull-downs. Leaving the pins
floating causes a high impedance
state.
• SMBus Input.
• Refer to Section 5.3.4.
SM_VCC • Connect to 3.3 V power supply.
SM_WP • Pull to VCC_SMBus with 100
Ω ± 5% resistor
to write-protect the processor’s Scratch
EEPROM. Leave as no connect (NC) to
disable write-protecting of Scratch
EEPROM.
• Pulling this signal to VCC_SMBus
enables write protection on the
processor scratchpad memory
device.
• SMBus Input.
• Refer to Section 5.3.4.
SMI# • Connect to both processors and ICH3-S.
Include 200
Ω ± 5% pull-up to VCC_CPU.
• Asserted asynchronously by
system logic.
• Asynchronous GTL+ Input
• Refer to Section 5.3.2.
STPCLK# • Connect to both processors and ICH3-S.
Include 200
Ω ± 5% pull-up to VCC_CPU.
• Causes processors to enter a low
power Stop-grant state.
• Asynchronous GTL+ Input.
• Refer to Section 5.3.2.
Table 13-1. Processor Schematic Checklist (Sheet 5 of 6)
Checklist Items Recommendations Comments

Intel Xeon Specifications

General

Brand	Intel
Model	Xeon
Category	Processor
Language	English