© 2004 Microchip Technology Inc. DS70061C-page 14-5
Section 14. Output Compare
Output
Compare
14
14.3.1.1 Compare Mode Output Driven High
To configure the output compare module for this mode, set control bits OCM<2:0> = ‘001’. The
compare time base should also be enabled. Once this Compare mode has been enabled, the
output pin, OCx, will be initially driven low and remain low until a match occurs between the TMRy
and OCxR registers. Referring to Figure 14-2, there are some key timing events to note:
• The OCx pin is driven high one instruction clock after the compare match occurs between
the compare time base and the OCxR register. The OCx pin will remain high until a mode
change has been made, or the module is disabled.
• The compare time base will count up to the value contained in the associated period
register and then reset to 0x0000 on the next instruction clock.
• The respective channel interrupt flag, OCxIF, is asserted 2 instruction clocks after the OCx
pin is driven high.
Figure 14-2: Single Compare Mode: Set OCx High on Compare Match Event
OCxIF
4000 0001
3001 3002 3003 30043000
TMRy
0000
Cleared by User
1 Instruction Clock Period
2 TCY
4000
3002
PRy
OCxR
3FFF
OCx pin
TMRy Resets Here
Note: An ‘x’ represents the output compare channel number. A ‘y’ represents the time base number.
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