dsPIC30F Family Reference Manual
DS70061C-page 14-6 © 2004 Microchip Technology Inc.
14.3.1.2 Compare Mode Output Driven Low
To configure the output compare module for this mode, set control bits OCM<2:0> = ‘010’. The
compare time base must also be enabled. Once this Compare mode has been enabled, the
output pin, OCx, will be initially driven high and remain high until a match occurs between the
Timer and OCxR registers. Referring to Figure 14-3, there are some key timing events to note:
• The OCx pin is driven low one instruction clock after the compare match occurs between
the compare time base and the OCxR register. The OCx pin will remain low until a mode
change has been made, or the module is disabled.
• The compare time base will count up to the value contained in the associated period
register and then reset to 0x0000 on the next instruction clock.
• The respective channel interrupt flag, OCxIF, is asserted 2 instruction clocks after OCx pin
is driven low.
Figure 14-3: Single Compare Mode: Force OCx Low on Compare Match Event
OCxIF
4C00 0001
47FF 4800 4801 480247FE
TMRy
0000
Cleared by User
1 Instruction Clock Period
2 TCY
4C00
4800
PRy
OCxR
4BFF
OCx pin
TMRy Resets Here
Note: An ‘x’ represents the output compare channel number. A ‘y’ represents the time base number.
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