Microchip Technology dsPIC30F - Page 537

© 2004 Microchip Technology Inc. DS70068C-page 21-23
Section 21. Inter-Integrated Circuit (I
2
C)
Inter-Integrated
Circuit (I
2
C)
21
21.5.6 Generating Repeated Start Bus Event
Setting the Repeated Start sequence enable bit, RSEN (I2CCON<1>), enables generation of a
master Repeated Start sequence (see Figure 21-14).
To generate a Repeated Start condition, software sets the RSEN bit (I2CCON<1>). The module
asserts the SCL pin low. When the module samples the SCL pin low, the module releases the
SDA pin for one baud rate generator count (T
BRG). When the baud rate generator times out, if
the module samples SDA high, the module de-asserts the SCL pin. When the module samples
SCL pin high, the baud rate generator reloads and begins counting. SDA and SCL must be
sampled high for one T
BRG. This action is then followed by assertion of the SDA pin low for one
T
BRG while SCL is high.
The following is the Repeated Start sequence:
• The slave detects the Start condition, sets the S bit (I2CSTAT<3>) and clears the P bit
(I2CSTAT<4>).
• The RSEN bit is automatically cleared.
• The module generates the MI2CIF interrupt.
21.5.6.1 IWCOL Status Flag
If the software writes the I2CTRN when a Repeated Start sequence is in progress, then IWCOL
is set and the contents of the buffer are unchanged (the write doesn’t occur).
Figure 21-14: Master Repeated Start Timing Diagram
Note: The lower 5 bits of I2CCON must be ‘0’ (master logic inactive) before attempting to
set the RSEN bit.
Note: Because queueing of events is not allowed, writing of the lower 5 bits of I2CCON is
disabled until the Repeated Start condition is complete.
SCL (Master)
SDA (Master)
S
RSEN
MI2CIF Interrupt
TBRG
1 2 3 5
- Writing RSEN = 1 initiates a master Repeated Start event.
1
TBRG
Baud generator starts. Module drives SCL low and
- Baud generator times out. Module releases SCL.
2
Baud generator restarts.
- Baud generator times out. Module drives SDA low.
3
- Slave logic detects Start. Module sets S = 1, P = 0.
4
I
2
C Bus State
(S) (Q)
P
TBRG
(Q)
4
Baud generator restarts.
- The baud generator times out. Module drives SCL low.
5
Module clears RSEN. Master generates interrupt.
(Q)
releases SDA.