© 2004 Microchip Technology Inc. DS70074C-page 26-7
Section 26. Appendix
Appendix
26
When a master does not wish to relinquish the bus (which occurs by generating a Stop
condition), a repeated Start condition (Sr) must be generated. This condition is identical to the
Start condition (SDA goes high-to-low, while SCL is high), but occurs after a data transfer
Acknowledge pulse (not the bus-free state). This allows a master to send “commands” to the
slave and then receive the requested information or to address a different slave device. This
sequence is illustrated in Figure A-8.
Figure A-8: Combined Format
Combined format:
S
Combined format - A master addresses a slave with a 10-bit address, then transmits
Slave Address R/W AData A/A Sr P
(read) Sr = repeated
Transfer direction of data and acknowledgment bits depends on R/W bits.
From master to slave
From slave to master
A = acknowledge (SDA low)
A
= not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
Slave Address
(Code + A9:A8)
Sr R/W A
(write)
data to this slave and reads data from this slave.
Slave Address
(A7:A0)
Data Sr Slave Address
(Code + A9:A8)
R/W
ADataA APA ADataA/A Data
(read)
Slave Address R/W
AData A/A
Start Condition
(write) Direction of transfer
may change at this point
(read or write)
(n bytes + acknowledge)
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