Schweitzer Engineering Laboratories SEL-351A - Figure 4.1 Loss-Of-Potential Logic

Date Code 20080213 Instruction Manual SEL-351A Relay
Section 4
Loss-of-Potential, Load Encroachment,
and Directional Element Logic
Loss-of-Potential Logic (Not in the SEL-351A-1)
The loss-of-potential (LOP) logic operates as shown in Figure 4.1.
q From Figure 5.3; w to Figure 4.6, Figure 4.7, Figure 4.8, and Figure 4.21; e to
Figure 4.15, Figure 4.16, and Figure 4.22.
Figure 4.1 Loss-of-Potential Logic
Inputs into the LOP logic are:
3PO three-pole open condition (indicates circuit breaker open
condition see Figure 5.3)
V
1
positive-sequence voltage (V secondary)
I
1
positive-sequence current (A secondary)
I
0
zero-sequence current (A secondary)
V
0
zero-sequence voltage (V secondary) {wye-connected
PTs}
V
2
negative-sequence voltage (V secondary) {delta-
connected PTs}
VNOM PT nominal voltage setting (line-to-neutral {wye-
connected PTs} or line-to-line {delta-connected PTs},
secondary)
LOP
ELOP = Y
ELOP = Y or Y1
3PO
Wye-Connected PTs
Delta-Connected PTs
VNOM
V
1
, I
1
, I
0
V
0
V
2
Loss-of-Potential
Logic
Relay
Word
Bits
Relay
Word
Bit
Settings
q
w
e
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