Schweitzer Engineering Laboratories SEL-351A - Section 5: Trip and Target Logic Trip Logic; Figure 5.1 Trip Logic

5.2
SEL-351A Relay Instruction Manual Date Code 20080213
Trip and Target Logic
Trip Logic
Figure 5.1 Trip Logic
Set Trip
Refer to Figure 5.1. All trip conditions:
➤ Direct Transfer Trip
➤ Switch-Onto-Fault Trip
➤ Other Trips
are combined into OR-1 gate. The output of OR-1 gate asserts Relay Word bit
TRIP to logical 1, regardless of other trip logic conditions. It also is routed
into the Minimum Trip Duration Timer (setting TDURD).
As shown in the time line example in Figure 5.2, the Minimum Trip Duration
Timer (with setting TDURD) outputs a logical 1 for a time duration of
“TDURD” cycles any time it sees a rising edge on its input (logical 0 to
logical 1 transition), if it is not already timing (timer is reset). The TDURD
timer ensures that the TRIP Relay Word bit remains asserted at logical 1 for a
minimum of “TDURD” cycles. If the output of OR-1 gate is logical 1 beyond
the TDURD time, Relay Word bit TRIP remains asserted at logical 1 for as
long as the output of OR-1 gate remains at logical 1, regardless of other trip
logic conditions.
The Minimum Trip Duration Timer can be set no less than 4 cycles.
Trip
Seal-in
and
Unlatch
Logic
"Other Trips"
Trip Logic
Switch-Onto-Fault
Trip Logic
Unlatch Trip
ULTR
Other Trips
TR
Switch-Onto-Fault Trip
TRSOTF
SOTFE
Direct Transfer Trip
DTT
TRIP
Serial Port
Command
{TARGET
RESET}
Pushbutton
TAR R
Rising Edge
Detect
Minimum Trip
Duration Timer
TRGTR
0
TDURD
SELOGIC
Trip
Settings
SELOGIC
Trip
Setting
SELOGIC
Setting
OR-2
OR-1
Relay
Word
Bit
Courtesy of NationalSwitchgear.com