7.13
Date Code 20080213 Instruction Manual SEL-351A Relay
Inputs, Outputs, Timers, and Other Control Logic
Latch Control Switches
Feedback Control
Note in Figure 7.13 that the latch control switch output (latch bit LT1) is
effectively used as feedback for SEL
OGIC control equation settings SET1 and
RST1. The feedback of latch bit LT1 “guides” input IN104 to the correct latch
control switch input.
If latch bit LT1 = logical 0, input IN104 is routed to setting SET1 (set latch bit
LT1):
SET1 = /IN104 * !LT1 = /IN104 * NOT(LT1) = /IN104 * NOT(logical 0)
= /IN104 = rising edge of input IN104
RST1 = /IN104 * LT1 = /IN104 * (logical 0) = logical 0
If latch bit LT1 = logical 1, input IN104 is routed to setting RST1 (reset latch
bit LT1):
SET1 = /IN104 * !LT1 = /IN104 * NOT(LT1) = /IN104 * NOT(logical 1)
= /IN104 * (logical 0) = logical 0
RST1 = /IN104 * LT1 = /IN104 * (logical 1) = /IN104 = rising edge of input
IN104
Rising-Edge Operators
Refer to Figure 7.13 and Figure 7.14.
The rising-edge operator in front of Relay Word bit IN104 (/IN104) sees a
logical 0 to logical 1 transition as a “rising edge,” and /IN104 asserts to
logical 1 for one processing interval.
The rising-edge operator on input IN104 is necessary because any single
assertion of optoisolated input IN104 by the SCADA contact will last for at
least a few cycles, and each individual assertion of input IN104 should only
change the state of the latch control switch once (e.g., latch bit LT1 changes
state from logical 0 to logical 1).
For example in Figure 7.13, if:
LT1 = logical 0
input IN104 is routed to setting SET1 (as discussed previously):
SET1 = /IN104 = rising edge of input IN104
If input IN104 is then asserted for a few cycles by the SCADA contact (see
Pulse 1 in Figure 7.14), SET1 is asserted to logical 1 for one processing
interval. This causes latch bit LT1 to change state to:
LT1 = logical 1
the next processing interval.
With latch bit LT1 now at logical 1 for the next processing interval, input
IN104 is routed to setting RST1 (as discussed previously):
RST1 = /IN104 = rising edge of input IN104
This would then appear to enable the “reset” input (setting RST1) the next
processing interval. But the “rising-edge” condition occurred during the
preceding processing interval. /IN104 is now at logical 0, so setting RST1
does not assert, even though input IN104 remains asserted for at least a few
cycles by the SCADA contact.
NOTE: Refer to Optoisolated Inputs
on page 7.2 and Figure 7.1. Relay Word
bit IN104 shows the state of
optoisolated input IN104 after the input
pickup/dropout debounce timer
IN104D. Thus, when using Relay Word
bit IN104 in Figure 7.11 and Figure 7.12
and associated SEL
OGIC control
equations, keep in mind any time
delay produced by the input pickup/
dropout debounce timer IN104D.
Courtesy of NationalSwitchgear.com
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