Embedded Flash memory (FLASH) for category 3 devices RM0440
100/2126 RM0440 Rev 4
If a loop is present in the current buffer, no new flash access is performed.
Instruction cache memory (I-Cache)
To limit the time lost due to jumps, it is possible to retain 32 lines of 4 x 64 bits in dual bank
mode or 32 lines of 2 x 128 bits in single bank mode in an instruction cache memory.This
feature can be enabled by setting the instruction cache enable (ICEN) bit in the Flash
access control register (FLASH_ACR). Each time a miss occurs (requested data not
present in the currently used instruction line, in the prefetched instruction line or in the
instruction cache memory), the line read is copied into the instruction cache memory. If
some data contained in the instruction cache memory are requested by the CPU, they are
provided without inserting any delay. Once all the instruction cache memory lines have been
filled, the LRU (least recently used) policy is used to determine the line to replace in the
instruction memory cache. This feature is particularly useful in case of code containing
loops.
The Instruction cache memory is enable after system reset.
Data cache memory (D-Cache)
Literal pools are fetched from Flash memory through the DCode bus during the execution
stage of the CPU pipeline. Each DCode bus read access fetches 64 or 128 bits which are
saved in a current buffer. The CPU pipeline is consequently stalled until the requested literal
pool is provided. To limit the time lost due to literal pools, accesses through the AHB
databus DCode have priority over accesses through the AHB instruction bus ICode.
If some literal pools are frequently used, the data cache memory can be enabled by setting
the data cache enable (DCEN) bit in the Flash access control register (FLASH_ACR). This
feature works like the instruction cache memory, but the retained data size is limited to 8
rows of 4*64 bits in dual bank mode and to 8 rows of 2*128 bits in single bank mode.
The Data cache memory is enable after system reset.
Note: The D-Cache is active only when data is requested by the CPU (not by DMA1 and DMA2).
Data in option bytes block are not cacheable.
3.3.5 Flash program and erase operations
The STM32G4 Series embedded Flash memory can be programmed using in-circuit
programming or in-application programming.
The in-circuit programming (ICP) method is used to update the entire contents of the
Flash memory, using the JTAG, SWD protocol or the boot loader to load the user application
into the microcontroller. ICP offers quick and efficient design iterations and eliminates
unnecessary package handling or socketing of devices.
In contrast to the ICP method, in-application programming (IAP) can use any
communication interface supported by the microcontroller (I/Os, USB, CAN, UART, I
2
C, SPI,
etc.) to download programming data into memory. IAP allows the user to re-program the
Flash memory while the application is running. Nevertheless, part of the application has to
have been previously programmed in the Flash memory using ICP.
The contents of the Flash memory are not guaranteed if a device reset occurs during a
Flash memory operation.
An on-going Flash memory operation does not block the CPU as long as the CPU does not
access the same Flash memory bank. Code or data fetches are possible on one bank while
To Next Page
General
