ST STM32G474 User Manual

RM0440 Rev 4 1881/2126
RM0440 Inter-integrated circuit (I2C) interface
1928
Figure 642. Master clock generation
Caution: In order to be I
2
C or SMBus compliant, the master clock must respect the timings given the
table below.
MS19858V1
t
SYNC1
SCL high level detected
SCLH counter starts
SCLH
SCL
SCL master clock generation
SCL released
SCL low level detected
SCLL counter starts
SCL driven low
SCLL
t
SYNC2
SCL master clock synchronization
SCLL
SCL driven low by
another device
SCL low level detected
SCLL counter starts
SCL released
SCLH
SCLH
SCL high level detected
SCLH counter starts
SCL high level detected
SCLH counter starts
SCL low level detected
SCLL counter starts
SCLL
SCL driven low by
another device
SCLH
SCL high level detected
SCLH counter starts

ST STM32G474 Specifications

General

Brand	ST
Model	STM32G474
Category	Microcontrollers
Language	English