ST STM32G474 - Figure 483. Counter Timing Diagram, Internal Clock Divided by 1; Figure 484. Counter Timing Diagram, Internal Clock Divided by 2

RM0440 Rev 4 1451/2126
RM0440 Basic timers (TIM6/TIM7)
1463
Figure 483. Counter timing diagram, internal clock divided by 1
Figure 484. Counter timing diagram, internal clock divided by 2
MSv50997V1
00
02
03
04 05
06 0732
33
34 35 36
31
tim_psc_ck
CEN
tim_cnt_ck
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag
(UIF)
01
MSv62300V1
tim_psc_ck
CEN
tim_cnt_ck
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag
(UIF)
0034
0035
0036
0000
0001
0002
0003