High-resolution timer (HRTIM) RM0440
870/2126 RM0440 Rev 4
have a master-slave system.The slave converter synchronization is continuously adjusted
based on the previous switching period of the master converter.
This is done using the capture unit. The switching period of the master converter is
captured, divided by 2 and then stored in the compare 2 register by hardware. The compare
2 register contains a value equal to half of the captured period, which is the master
converter switching period. The compare 2 event can then be used to trigger a second
timing unit that manages the slave converter.
This mode is enabled by setting the TRGHLF bit in the HRTIM_TIMxCR2 register. This bit
cannot be changed once the timer is operating (TxEN bit set).
The triggered-half mode must not be used simultaneously with other modes using CMP2
(dual channel dac trigger, interleaved and balanced idle modes).
The initial value CMP2 can be written by the user, but is ignored once the first capture is
triggered. The preload mechanism is disabled for CMP2 when the TRGHLF bit is reset.
Figure 194. Triggered-half mode example
MSv45796V2
CMP1
CMP2
Capture
Master
(HRTIM_CHA1)
Slave
(HRTIM_CHB1)
Blanking
(HRTIM_CHA2)
HRTIM_CHA1
Set on EEV1 (EEV1 triggers Capture1)
Reset on EEV2
EEV1 Blanking on TIMA_CMP1 (avoid frequency run-away)
HRTIM_CHB1
Set on CMP2 (triggered-half) or EEV1 blanking by TIMA_TA2
(TB1 is set if EEV1 occurs between CMP1 and CMP2, else on CMP2)
Reset on EEV3
HRTIM_CHA2
Set on TA_CMP1
Reset on TA_CMP2
EEV3
EEV3 EEV3
EEV2 EEV2 EEV2
Capture
Capture
EEV1EEV1
EEV1
To Next Page
General
