Inter-integrated circuit (I2C) interface RM0440
1860/2126 RM0440 Rev 4
The following additional features are also available depending on the product
implementation (see Section 41.3: I2C implementation):
• SMBus specification rev 3.0 compatibility:
– Hardware PEC (Packet Error Checking) generation and verification with ACK
control
– Command and data acknowledge control
– Address resolution protocol (ARP) support
– Host and Device support
– SMBus alert
– Timeouts and idle condition detection
• PMBus rev 1.3 standard compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming
• Wakeup from Stop mode on address match.
41.3 I2C implementation
This manual describes the full set of features implemented in I2C peripheral. In the
STM32G4 Series devices I2C1, I2C2, I2C3 and I2C4 implement the full set of features as
shown in the following table.
41.4 I2C functional description
In addition to receiving and transmitting data, this interface converts it from serial to parallel
format and vice versa. The interrupts are enabled or disabled by software. The interface is
connected to the I
2
C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected
with a standard (up to 100 kHz), Fast-mode (up to 400 kHz) or Fast-mode Plus (up to
1MHz) I
2
C bus.
This interface can also be connected to a SMBus with the data pin (SDA) and clock pin
(SCL).
Table 373. I2C implementation
I2C features
(1)
I2C1 I2C2 I2C3 I2C4
7-bit addressing mode XXXX
10-bit addressing mode XXXX
Standard-mode (up to 100 kbit/s) XXXX
Fast-mode (up to 400 kbit/s) XXXX
Fast-mode Plus with 20mA output drive I/Os
(up to 1 Mbit/s)
XXXX
Independent clock XXXX
Wakeup from Stop 1 mode XXXX
SMBus/PMBus XXXX
1. X = supported.
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