RM0440 Rev 4 779/2126
RM0440 Comparator (COMP)
785
24.3.2 COMP pins and internal signals
The I/Os used as comparators inputs must be configured in analog mode in the GPIOs
registers.
The comparator output can be connected to the I/Os using the alternate function channel
given in “Alternate function mapping” table in the datasheet.
The output can also be internally redirected to a variety of timer input for the following
purposes:
• Emergency shut-down of PWM signals, using BKIN and BKIN2 inputs
• Cycle-by-cycle current control, using OCREF_CLR inputs
• Input capture for timing measures
It is possible to have the comparator output simultaneously redirected internally and
externally.
24.3.3 COMP reset and clocks
The COMP clock provided by the clock controller is synchronous with the APB2 clock.
There is no COMP-dedicated clock enable control bit in the RCC controller. Reset and clock
enable bits are common for COMP and SYSCFG.
Note: Important: The polarity selection logic and the output redirection to the port works
independently of APB clock. This allows the comparator to work even in Stop mode.
Table 195. COMPx non-inverting input assignment
INPSEL
COMP1_
INP
COMP2_
INP
COMP3_
INP
COMP4_
INP
COMP5_
INP
COMP6_
INP
COMP7_
INP
0 PA1 PA7 PA0 PB0 PB13 PB11 PB14
1 PB1 PA3 PC1 PE7 PD12 PD11 PD14
Table 196. COMPx inverting input assignment
INMSEL
[2:0]
COMP1_
INM
COMP2_
INM
COMP3_
INM
COMP4_
INM
COMP5_
INM
COMP6_
INM
COMP7_
INM
000 1/4 V
REFINT
001 1/2 V
REFINT
010 3/4 V
REFINT
011 V
REFINT
100 DAC3_CH1 DAC3_CH2 DAC3_CH1 DAC3_CH2 DAC4_CH1 DAC4_CH2 DAC4_CH1
101 DAC1_CH1 DAC1_CH2 DAC1_CH1 DAC1_CH1 DAC1_CH2 DAC2_CH1 DAC2_CH1
110 PA4 PA5 PF1 PE8 PB10 PD10 PD15
111 PA0 PA2 PC0 PB2 PD13 PB15 PB12
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