ST STM32G474

RM0440 Rev 4 1877/2126
RM0440 Inter-integrated circuit (I2C) interface
1928
Figure 638. Transfer bus diagrams for I2C slave transmitter
MS19853V2
Example I2C slave transmitter 3 bytes with 1st data flushed,
NOSTRETCH=0:
EV1: ADDR ISR: check ADDCODE and DIR, set TXE, set ADDRCF
EV2: TXIS ISR: wr data1
EV3: TXIS ISR: wr data2
EV4: TXIS ISR: wr data3
EV5: TXIS ISR: wr data4 (not sent)
ADDR
A
TXIS
A
TXIS
NA
TXIS
TXE
P
legend:
transmission
reception
SCL stretch
EV1
EV2
EV4 EV5
Example I2C slave transmitter 3 bytes, NOSTRETCH=1:
EV1: wr data1
EV2: TXIS ISR: wr data2
EV3: TXIS ISR: wr data3
EV4: TXIS ISR: wr data4 (not sent)
EV5: STOPF ISR: (optional: set TXE and TXIS), set STOPCF
A
TXIS
TXIS
TXE
legend:
transmission
reception
SCL stretch
EV2 EV3 EV4
TXIS
EV1
STOPF
EV5
Example I2C slave transmitter 3 bytes without 1st data flush,
NOSTRETCH=0:
EV1: ADDR ISR: check ADDCODE and DIR, set ADDRCF
EV2: TXIS ISR: wr data2
EV3: TXIS ISR: wr data3
EV4: TXIS ISR: wr data4 (not sent)
ADDR
TXIS
TXIS TXIS
TXE
legend :
transmission
reception
SCL stretch
EV1
EV2
EV3 EV4
TXIS
EV3
S Address data1 A data2 data3ANAP
S Address A data1 A data2 A data3 NA P
A
data3
data2
data1
S Address