ST STM32G474 - Table 407. STM32 G4 Series USB Implementation

RM0440 Rev 4 2009/2126
RM0440 Universal serial bus full-speed device interface (USB)
2041
45 Universal serial bus full-speed device interface (USB)
45.1 Introduction
The USB peripheral implements an interface between a full-speed USB 2.0 bus and the
APB1 bus.
USB suspend/resume are supported, which allows to stop the device clocks for low-power
consumption.
45.2 USB main features
• USB specification version 2.0 full-speed compliant
• Configurable number of endpoints from 1 to 8
• Dedicated packet buffer memory (SRAM) of 1024 bytes
• Cyclic redundancy check (CRC) generation/checking, Non-return-to-zero Inverted
(NRZI) encoding/decoding and bit-stuffing
• Isochronous transfers support
• Double-buffered bulk/isochronous endpoint support
• USB Suspend/Resume operations
• Frame locked clock pulse generation
• USB 2.0 Link Power Management support
• Battery Charging Specification Revision 1.2 support
• USB connect / disconnect capability (controllable embedded pull-up resistor on
USB_DP line)
45.3 USB implementation
Table 407 describes the USB implementation in the devices.
Table 407. STM32G4 Series USB implementation
USB features
(1)
1. X= supported
USB
Number of endpoints 8
Size of dedicated packet buffer memory SRAM 1024 bytes
Dedicated packet buffer memory SRAM access scheme 2 x 16 bits / word
USB 2.0 Link Power Management (LPM) support X
Battery Charging Detection (BCD) support X
Embedded pull-up resistor on USB_DP line X