Flexible static memory controller (FSMC) RM0440
532/2126 RM0440 Rev 4
Note: The FMC_BWTRx register is valid only if the Extended mode is set (mode B), otherwise its
content is don’t care.
3:2 MTYP 0x2 (NOR Flash memory)
1 MUXEN 0x0
0 MBKEN 0x1
Table 135. FMC_BTRx bitfields (mode 2/B)
Bit number Bit name Value to set
31:30 DATAHLD
Duration of the data hold phase (DATAHLD HCLK cycles for read
accesses and DATAHLD+1 HCLK cycles for write accesses when
Extended mode is disabled).
29:28 ACCMOD 0x1 if Extended mode is set
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15:8 DATAST
Duration of the access second phase (DATAST HCLK cycles) for
read accesses.
7:4 ADDHLD Don’t care
3:0 ADDSET
Duration of the access first phase (ADDSET HCLK cycles) for read
accesses. Minimum value for ADDSET is 0.
Table 136. FMC_BWTRx bitfields (mode 2/B)
Bit number Bit name Value to set
31:30 DATAHLD
Duration of the data hold phase (DATAHLD+1 HCLK cycles for write
accesses).
29:28 ACCMOD 0x1 if Extended mode is set
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15:8 DATAST
Duration of the access second phase (DATAST HCLK cycles) for
write accesses.
7:4 ADDHLD Don’t care
3:0 ADDSET
Duration of the access first phase (ADDSET HCLK cycles) for write
accesses. Minimum value for ADDSET is 0.
Table 134. FMC_BCRx bitfields (mode 2/B) (continued)
Bit number Bit name Value to set
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